0e805e1ff3
dev/alpha_access.h:
removed my attempted hack to get console compling in linux
dev/tsunami.cc:
dev/tsunami.hh:
added pchip pointer to tsunami
dev/tsunami_cchip.cc:
made printing better
dev/tsunami_cchip.hh:
commented out back pointer for now, since the parser has issues with it
dev/tsunamireg.h:
added pchip registers
--HG--
extra : convert_revision : b4fceb7d08e757d9aaf37df8eb1bcd5ae29ce0da
258 lines
7.9 KiB
C++
258 lines
7.9 KiB
C++
/* $Id$ */
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/* @file
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* Tsunami PChip (pci)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/etherdev.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiPChip::TsunamiPChip(const string &name, /*Tsunami *t,*/
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
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{
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wsba0 = 0;
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wsba1 = 0;
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wsba2 = 0;
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wsba3 = 0;
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wsm0 = 0;
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wsm1 = 0;
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wsm2 = 0;
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wsm3 = 0;
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tba0 = 0;
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tba1 = 0;
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tba2 = 0;
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tba3 = 0;
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}
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Fault
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TsunamiPChip::read(MemReqPtr req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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*(uint64_t*)data = wsba0;
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return No_Fault;
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case TSDEV_PC_WSBA1:
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*(uint64_t*)data = wsba1;
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return No_Fault;
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case TSDEV_PC_WSBA2:
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*(uint64_t*)data = wsba2;
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return No_Fault;
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case TSDEV_PC_WSBA3:
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*(uint64_t*)data = wsba3;
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return No_Fault;
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case TSDEV_PC_WSM0:
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*(uint64_t*)data = wsm0;
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return No_Fault;
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case TSDEV_PC_WSM1:
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*(uint64_t*)data = wsm1;
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return No_Fault;
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case TSDEV_PC_WSM2:
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*(uint64_t*)data = wsm2;
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return No_Fault;
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case TSDEV_PC_WSM3:
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*(uint64_t*)data = wsm3;
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return No_Fault;
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case TSDEV_PC_TBA0:
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*(uint64_t*)data = tba0;
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return No_Fault;
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case TSDEV_PC_TBA1:
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*(uint64_t*)data = tba1;
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return No_Fault;
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case TSDEV_PC_TBA2:
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*(uint64_t*)data = tba2;
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return No_Fault;
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case TSDEV_PC_TBA3:
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*(uint64_t*)data = tba3;
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return No_Fault;
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case TSDEV_PC_PCTL:
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// might want to change the clock??
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*(uint64_t*)data = 0x00; // try this
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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panic("PC_PERROR not implemented\n");
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
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return No_Fault;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiPChip::write(MemReqPtr req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba0 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA1:
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wsba1 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA2:
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wsba2 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA3:
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wsba3 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM0:
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wsm0 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM1:
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wsm1 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM2:
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wsm2 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM3:
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wsm3 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA0:
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tba0 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA1:
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tba1 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA2:
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tba2 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA3:
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tba3 = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_PCTL:
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// might want to change the clock??
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//*(uint64_t*)data; // try this
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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panic("PC_PERROR not implemented\n");
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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return No_Fault; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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void
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TsunamiPChip::serialize(std::ostream &os)
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{
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// code should be written
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}
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void
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TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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/* SimObjectParam<Tsunami *> tsunami;*/
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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/*INIT_PARAM(tsunami, "Tsunami"),*/
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask")
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END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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CREATE_SIM_OBJECT(TsunamiPChip)
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{
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return new TsunamiPChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
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