10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
951 lines
106 KiB
Text
951 lines
106 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000020 # Number of seconds simulated
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sim_ticks 20334000 # Number of ticks simulated
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final_tick 20334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 80964 # Simulator instruction rate (inst/s)
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host_op_rate 80958 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 129154883 # Simulator tick rate (ticks/s)
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host_mem_usage 217900 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
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sim_insts 12745 # Number of instructions simulated
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 22784 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62656 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 356 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 979 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1960853743 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1120487853 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3081341595 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1960853743 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1960853743 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1960853743 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1120487853 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3081341595 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 979 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 979 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 62656 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 62656 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 73 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 81 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 76 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 99 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 76 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 20181000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 979 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 49 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 11431477 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 34163477 # Sum of mem lat for all requests
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system.physmem.totBusLat 3916000 # Total cycles spent in databus access
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system.physmem.totBankLat 18816000 # Total cycles spent in bank access
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system.physmem.avgQLat 11676.69 # Average queueing delay per request
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system.physmem.avgBankLat 19219.61 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 34896.30 # Average memory access latency
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system.physmem.avgRdBW 3081.34 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 3081.34 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 19.26 # Data bus utilization in percentage
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system.physmem.avgRdQLen 1.68 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 740 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 75.59 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 20613.89 # Average gap between requests
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4607 # DTB read hits
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system.cpu.dtb.read_misses 109 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4716 # DTB read accesses
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system.cpu.dtb.write_hits 2105 # DTB write hits
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system.cpu.dtb.write_misses 77 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 2182 # DTB write accesses
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system.cpu.dtb.data_hits 6712 # DTB hits
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system.cpu.dtb.data_misses 186 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 6898 # DTB accesses
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system.cpu.itb.fetch_hits 5687 # ITB hits
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system.cpu.itb.fetch_misses 59 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 5746 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload0.num_syscalls 17 # Number of system calls
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system.cpu.workload1.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 40669 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 6981 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 3954 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 1690 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 5146 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 870 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 937 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 1717 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 38666 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6981 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1807 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 6508 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2004 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 376 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 5687 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 27168 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.423218 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.808405 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 20660 76.05% 76.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 537 1.98% 78.02% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 399 1.47% 79.49% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 504 1.86% 81.35% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 464 1.71% 83.05% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 436 1.60% 84.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 485 1.79% 86.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 591 2.18% 88.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 3092 11.38% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 27168 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.171654 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.950749 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 38149 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 6961 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 5575 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 2929 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 646 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 395 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 33907 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 2929 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 38897 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 984 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 5237 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 2250 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 31157 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
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system.cpu.rename.LSQFullEvents 2290 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 23416 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 38564 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 38530 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 14276 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 53 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 6217 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 3020 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1445 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 2972 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1380 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 27184 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 71 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 22298 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 13301 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 8222 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 27168 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.820745 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.402255 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 17752 65.34% 65.34% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 3320 12.22% 77.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 2545 9.37% 86.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1596 5.87% 92.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1085 3.99% 96.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 559 2.06% 98.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 231 0.85% 99.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 61 0.22% 99.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 19 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 27168 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 13 6.70% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 118 60.82% 67.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 63 32.47% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 7510 66.63% 66.65% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2596 23.03% 89.71% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1160 10.29% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 11271 # Type of FU issued
|
|
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntAlu 7311 66.30% 66.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2558 23.20% 89.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1153 10.46% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 11027 # Type of FU issued
|
|
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntAlu 14821 66.47% 66.49% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntMult 2 0.01% 66.49% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntDiv 0 0.00% 66.49% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatMult 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMult 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShift 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemRead 5154 23.11% 89.63% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemWrite 2313 10.37% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::total 22298 # Type of FU issued
|
|
system.cpu.iq.rate 0.548280 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 100 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 94 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.004485 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.004216 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.008700 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 72061 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 40564 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 19339 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 22466 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1837 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 580 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 295 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 77 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1789 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 515 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2929 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 685 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 27441 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 749 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 5992 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2825 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 71 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 275 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1233 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1508 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20701 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2373 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2359 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4732 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1597 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 114 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 72 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 186 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3487 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 3445 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6932 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1642 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1642 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 3284 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1114 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1086 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2200 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.509012 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9936 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 9721 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 19657 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9778 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 19359 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 5047 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 4925 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 9972 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6570 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 6411 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 12981 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate::0 0.240429 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.235585 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.476014 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.768189 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.768211 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.768200 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 14694 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1316 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 27077 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.251708 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 21479 79.33% 79.33% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 2818 10.41% 89.73% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1191 4.40% 94.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 503 1.86% 95.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 353 1.30% 97.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 251 0.93% 98.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 184 0.68% 98.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 85 0.31% 99.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 213 0.79% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 27077 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 129384 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 57896 # The number of ROB writes
|
|
system.cpu.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 13501 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
|
system.cpu.cpi::0 6.382454 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 6.381453 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.190977 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.156680 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.156704 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.313384 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 26029 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 14619 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.tagsinuse 309.378150 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 4652 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 7.443200 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 309.378150 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.151064 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.151064 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4652 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4652 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4652 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4652 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4652 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4652 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1030 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 56036996 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 56036996 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 56036996 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 56036996 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 56036996 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 56036996 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5682 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5682 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5682 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5682 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5682 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5682 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181274 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.181274 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.181274 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.181274 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.181274 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.181274 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54404.850485 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54404.850485 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 54404.850485 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 54404.850485 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 2136 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 38.142857 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37870497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 37870497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37870497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 37870497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37870497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 37870497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109996 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.109996 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.109996 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60592.795200 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60592.795200 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 213.566251 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 4636 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 356 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 13.022472 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 213.566251 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.052140 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.052140 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3620 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3620 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1016 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1016 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4636 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4636 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4636 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4636 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 336 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 336 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 714 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 714 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1050 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1050 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1050 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1050 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20070500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 20070500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 32974457 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 32974457 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 53044957 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 53044957 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 53044957 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 53044957 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3956 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3956 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5686 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5686 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5686 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5686 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084934 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.084934 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.184664 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.184664 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.184664 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.184664 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59733.630952 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 59733.630952 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46182.712885 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 46182.712885 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 50519.006667 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 50519.006667 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2851 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 107 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.644860 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 694 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 694 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 694 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 694 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 356 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 356 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14343000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 14343000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8833995 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8833995 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23176995 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 23176995 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23176995 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 23176995 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053084 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053084 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062610 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.062610 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062610 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.062610 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60506.815068 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60506.815068 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65103.918539 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65103.918539 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65103.918539 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65103.918539 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 429.985619 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 833 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002401 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 309.894864 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 120.090755 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.009457 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003665 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.013122 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 623 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 210 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 833 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 623 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 356 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 979 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 623 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 356 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 979 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37222000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14122000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 51344000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8685000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8685000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 37222000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 22807000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 60029000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 37222000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 22807000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 60029000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 210 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 835 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 356 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 981 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 356 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 981 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996800 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997605 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996800 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997961 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996800 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997961 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59746.388443 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67247.619048 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 61637.454982 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59486.301370 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59486.301370 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59746.388443 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64064.606742 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 61316.649642 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59746.388443 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64064.606742 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 61316.649642 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 833 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 356 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 979 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29496155 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11535670 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41031825 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6881648 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6881648 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29496155 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18417318 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 47913473 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29496155 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18417318 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 47913473 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47345.353130 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54931.761905 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49257.893157 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 47134.575342 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 47134.575342 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|