10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
788 lines
90 KiB
Text
788 lines
90 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000014 # Number of seconds simulated
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sim_ticks 14081500 # Number of ticks simulated
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final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 87308 # Simulator instruction rate (inst/s)
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host_op_rate 87279 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 212126284 # Simulator tick rate (ticks/s)
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host_mem_usage 214180 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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sim_insts 5792 # Number of instructions simulated
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sim_ops 5792 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 453 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 453 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28992 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 13946000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 453 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 1940453 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests
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system.physmem.totBusLat 1812000 # Total cycles spent in databus access
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system.physmem.totBankLat 7462000 # Total cycles spent in bank access
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system.physmem.avgQLat 4283.56 # Average queueing delay per request
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system.physmem.avgBankLat 16472.41 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 24755.97 # Average memory access latency
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system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 12.87 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.80 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 376 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 30785.87 # Average gap between requests
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 9 # Number of system calls
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system.cpu.numCycles 28164 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2468 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2216 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 2079 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 9281 # Type of FU issued
|
|
system.cpu.iq.rate 0.329534 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 8398 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3302 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1388 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1577 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.312314 # Inst execution rate
|
|
system.cpu.iew.wb_sent 8586 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8425 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 4372 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 7073 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5792 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2007 # Number of memory references committed
|
|
system.cpu.commit.loads 961 # Number of loads committed
|
|
system.cpu.commit.membars 7 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1037 # Number of branches committed
|
|
system.cpu.commit.fp_insts 22 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 5698 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 103 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 21870 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 22837 # The number of ROB writes
|
|
system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
|
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5792 # Number of Instructions Simulated
|
|
system.cpu.cpi 4.862569 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 4.862569 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.205653 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 13961 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 7286 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 171.601938 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1437 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 4.036517 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 171.601938 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.083790 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.083790 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1437 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1437 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1437 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1437 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1437 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1437 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 440 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 440 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 440 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 440 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 440 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 440 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20404500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 20404500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 20404500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 20404500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 20404500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 20404500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1877 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1877 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1877 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1877 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1877 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1877 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234417 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.234417 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.234417 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.234417 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.234417 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.234417 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46373.863636 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 46373.863636 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 46373.863636 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 46373.863636 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 338 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 56.333333 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 84 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 84 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 84 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17051500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 17051500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17051500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 17051500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17051500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 17051500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189664 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.189664 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.189664 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47897.471910 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47897.471910 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 63.108123 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2206 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 21.627451 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 63.108123 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.015407 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.015407 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1490 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1490 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 716 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 716 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2206 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 330 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 330 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 427 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 427 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 427 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 427 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4870000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4870000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14038497 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 14038497 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 18908497 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 18908497 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 18908497 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 18908497 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1587 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1587 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2633 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2633 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2633 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2633 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061122 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.061122 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315488 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.315488 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.162172 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.162172 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.162172 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.162172 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.185567 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.185567 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42540.900000 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42540.900000 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 44282.194379 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 44282.194379 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 416 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.200000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3072500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3072500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2817999 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2817999 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5890499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5890499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5890499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5890499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034657 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034657 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.038739 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.038739 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55863.636364 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55863.636364 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59957.425532 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59957.425532 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 202.387362 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 170.963901 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31.423461 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005217 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.006176 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 5 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 453 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 453 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16645000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3017000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 19662000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2768500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2768500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 16645000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 5785500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 22430500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 16645000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 5785500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 22430500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47421.652422 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54854.545455 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48428.571429 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58904.255319 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58904.255319 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 49515.452539 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 49515.452539 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12250512 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2337054 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14587566 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2189544 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2189544 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12250512 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4526598 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 16777110 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12250512 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4526598 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 16777110 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34901.743590 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42491.890909 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35929.965517 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46586.042553 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46586.042553 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|