10b70d5452
This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
857 lines
98 KiB
Text
857 lines
98 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.027092 # Number of seconds simulated
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sim_ticks 27092156000 # Number of ticks simulated
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final_tick 27092156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 163409 # Simulator instruction rate (inst/s)
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host_op_rate 164582 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48864627 # Simulator tick rate (ticks/s)
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host_mem_usage 366512 # Number of bytes of host memory used
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host_seconds 554.43 # Real time elapsed on the host
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sim_insts 90599363 # Number of instructions simulated
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sim_ops 91249916 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 45696 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory
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system.physmem.bytes_read::total 993280 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 45696 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 45696 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 714 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1686687 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 34976323 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 36663011 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1686687 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1686687 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1686687 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 34976323 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 36663011 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15520 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 15520 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 993280 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 993280 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1012 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1000 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 965 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 878 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 903 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 974 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 937 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 992 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 942 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1013 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1040 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 931 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 935 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1022 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 999 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 977 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 27092026500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 15520 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 10854 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4463 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 41952001 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 275602001 # Sum of mem lat for all requests
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system.physmem.totBusLat 62080000 # Total cycles spent in databus access
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system.physmem.totBankLat 171570000 # Total cycles spent in bank access
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system.physmem.avgQLat 2703.09 # Average queueing delay per request
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system.physmem.avgBankLat 11054.77 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 17757.86 # Average memory access latency
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system.physmem.avgRdBW 36.66 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 36.66 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.23 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.01 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 15093 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 97.25 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 1745620.26 # Average gap between requests
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 54184313 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 26986209 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 22240935 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 891955 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 11647054 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 11461257 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 72758 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 485 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 14421407 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 129482789 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 26986209 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 11534015 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 24364148 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 4949387 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 11145499 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 14072424 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 353920 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 53972527 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.416768 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.215873 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 29646325 54.93% 54.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3454402 6.40% 61.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2035756 3.77% 65.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1585198 2.94% 68.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1689643 3.13% 71.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 2992855 5.55% 76.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 1501294 2.78% 79.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1109449 2.06% 81.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 9957605 18.45% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 53972527 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.498045 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.389673 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 17207234 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 9007840 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 22744655 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 980413 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 4032385 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 4494708 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 9020 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 127545337 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 43010 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 4032385 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 19020781 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 3479230 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 185856 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 21813074 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 5441201 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 124457435 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 413531 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4571711 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 1235 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 145128165 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 542105971 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 542097092 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 8879 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107429490 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 37698675 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 6572 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 6570 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12467133 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 29726886 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5575716 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2113972 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1267479 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 119141743 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 10445 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 105694934 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 87169 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 27699731 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 68149614 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 314 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 53972527 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.958310 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.906959 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 15655199 29.01% 29.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 11785517 21.84% 50.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 8331092 15.44% 66.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 6816137 12.63% 78.91% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 4950230 9.17% 88.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2999113 5.56% 93.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 2477964 4.59% 98.23% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 523647 0.97% 99.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 433628 0.80% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 53972527 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 46062 6.88% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 27 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.88% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 347309 51.84% 58.72% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 276528 41.28% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 74789995 70.76% 70.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10964 0.01% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 273 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 352 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 25743831 24.36% 95.13% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5149514 4.87% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 105694934 # Type of FU issued
|
|
system.cpu.iq.rate 1.950656 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 669926 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006338 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 266118166 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 146855539 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 103065096 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 1324 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1913 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 572 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 106364200 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 660 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 431890 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 7151007 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 8111 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 6407 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 828959 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 30712 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 4032385 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 880978 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 122273 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 119164915 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 339993 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 29726886 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5575716 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6543 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 65097 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 6980 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 6407 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 480710 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 474427 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 955137 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 104665581 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 25412111 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1029353 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12727 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 30497033 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 21398144 # Number of branches executed
|
|
system.cpu.iew.exec_stores 5084922 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.931658 # Inst execution rate
|
|
system.cpu.iew.wb_sent 103359257 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 103065668 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 62382767 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 104584630 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.902131 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.596481 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 27905407 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 10131 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 883062 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 49940143 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.827438 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.524426 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 20246507 40.54% 40.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13253757 26.54% 67.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4242903 8.50% 75.58% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3506121 7.02% 82.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1547134 3.10% 85.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 741508 1.48% 87.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 927602 1.86% 89.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 253977 0.51% 89.55% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5220634 10.45% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 49940143 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90611972 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91262525 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27322636 # Number of memory references committed
|
|
system.cpu.commit.loads 22575879 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18734217 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72533326 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5220634 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 163881707 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 242387570 # The number of ROB writes
|
|
system.cpu.timesIdled 40508 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 211786 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90599363 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91249916 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 90599363 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.598065 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.598065 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.672059 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.672059 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 497610089 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 120987803 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 263 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 760 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 183141130 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 11610 # number of misc regfile writes
|
|
system.cpu.icache.replacements 2 # number of replacements
|
|
system.cpu.icache.tagsinuse 641.121517 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 14071405 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 743 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 18938.633917 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 641.121517 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.313048 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.313048 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 14071405 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 14071405 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 14071405 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 14071405 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 14071405 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 14071405 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1017 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1017 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1017 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1017 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1017 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 47244499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 47244499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 47244499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 47244499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 47244499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 47244499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 14072422 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 14072422 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 14072422 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 14072422 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 14072422 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 14072422 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46454.767945 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 46454.767945 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 46454.767945 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46454.767945 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 46454.767945 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 274 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 274 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 274 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 274 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 274 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 743 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 743 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 743 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 743 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36064499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 36064499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36064499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 36064499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36064499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 36064499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48539.029610 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48539.029610 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48539.029610 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 48539.029610 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 943610 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3668.756958 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 28277834 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 947706 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 29.838192 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 8133068000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3668.756958 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.895693 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.895693 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23721969 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23721969 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4544209 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4544209 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5856 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5856 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5800 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5800 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 28266178 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 28266178 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 28266178 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 28266178 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1182969 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1182969 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 190772 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 190772 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1373741 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1373741 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1373741 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1373741 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 13927378500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 13927378500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5211268429 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 5211268429 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 191000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 191000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 19138646929 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 19138646929 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 19138646929 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 19138646929 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 24904938 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 24904938 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5862 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5862 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5800 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5800 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 29639919 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 29639919 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 29639919 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 29639919 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047499 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.047499 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040290 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.040290 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001024 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001024 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.046348 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.046348 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.046348 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.046348 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11773.240465 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11773.240465 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27316.736361 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 27316.736361 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 31833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 31833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13931.772386 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13931.772386 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13931.772386 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 151113 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 23634 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.393882 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 942971 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 942971 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 275787 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 275787 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150248 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 150248 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 426035 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 426035 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 426035 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 426035 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907182 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 907182 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40524 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 40524 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 947706 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 947706 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 947706 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 947706 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10023226500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10023226500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 922752968 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 922752968 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10945979468 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10945979468 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10945979468 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10945979468 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036426 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036426 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.008558 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.008558 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.031974 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031974 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.031974 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11048.749314 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11048.749314 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22770.530254 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22770.530254 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11549.973798 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11549.973798 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 10724.733108 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1834762 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 15503 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 118.348836 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 9870.615236 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 623.470728 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 230.647144 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.301227 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.019027 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.007039 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.327293 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 906888 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 906916 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 942971 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 942971 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 26002 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 26002 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 932890 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 932918 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 932890 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 932918 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 715 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 279 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 994 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 14537 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 14537 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 715 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 14816 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 715 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 14816 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 15531 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35034500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14031000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 49065500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 601080500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 601080500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 35034500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 615111500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 650146000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 35034500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 615111500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 650146000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 743 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 907167 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 907910 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 942971 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 942971 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 40539 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 40539 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 743 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 947706 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 948449 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 743 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 947706 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 948449 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962315 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358593 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.358593 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962315 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015634 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.016375 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962315 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015634 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.016375 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48999.300699 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 50290.322581 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49361.670020 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41348.318085 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41348.318085 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 41861.180864 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48999.300699 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41516.704914 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 41861.180864 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 714 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 269 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 983 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14537 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 14537 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 714 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 15520 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 714 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 14806 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15520 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26001093 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10248888 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 36249981 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 418962782 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 418962782 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26001093 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 429211670 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 455212763 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26001093 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 429211670 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 455212763 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358593 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358593 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960969 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36416.096639 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38099.955390 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36876.888098 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 28820.443145 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 28820.443145 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36416.096639 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 28989.036202 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29330.719265 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|