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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Andreas Hansson b387d8e213 stats: Update the stats to reflect the 1GHz default system clock 
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
2012-10-25 13:15:59 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.896908 # Number of seconds simulated
sim_ticks 1896907607500 # Number of ticks simulated
final_tick 1896907607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91997 # Simulator instruction rate (inst/s)
host_op_rate 91997 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3111116066 # Simulator tick rate (ticks/s)
host_mem_usage 330780 # Number of bytes of host memory used
host_seconds 609.72 # Real time elapsed on the host
sim_insts 56092592 # Number of instructions simulated
sim_ops 56092592 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 788928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24066944 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2649408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 193664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1095360 # Number of bytes read from this memory
system.physmem.bytes_read::total 28794304 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 788928 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 193664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 982592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7762048 # Number of bytes written to this memory
system.physmem.bytes_written::total 7762048 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12327 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 376046 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41397 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3026 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 17115 # Number of read requests responded to by this memory
system.physmem.num_reads::total 449911 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 121282 # Number of write requests responded to by this memory
system.physmem.num_writes::total 121282 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 415902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12687462 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1396698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 102095 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 577445 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15179603 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 415902 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 102095 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 517997 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4091948 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4091948 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4091948 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 415902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12687462 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1396698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 102095 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 577445 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19271551 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 449911 # Total number of read requests seen
system.physmem.writeReqs 121282 # Total number of write requests seen
system.physmem.cpureqs 578344 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28794304 # Total number of bytes read from memory
system.physmem.bytesWritten 7762048 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28794304 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7762048 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 53 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3357 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28022 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27737 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27975 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 28585 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 28318 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 28204 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 28175 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28470 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28412 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 28316 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 28619 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 28149 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27813 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27389 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27281 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7339 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7747 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7422 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7940 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7694 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7599 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7607 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7865 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7795 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7764 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 8092 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7767 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7407 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 6913 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 6820 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 313 # Number of times wr buffer was full causing retry
system.physmem.totGap 1896888917000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 449911 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 121595 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 3357 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 322755 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66156 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2879 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2466 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1798 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1693 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1579 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1787 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1472 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 908 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4069 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 4980 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 6417421318 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13706967318 # Sum of mem lat for all requests
system.physmem.totBusLat 1799432000 # Total cycles spent in databus access
system.physmem.totBankLat 5490114000 # Total cycles spent in bank access
system.physmem.avgQLat 14265.44 # Average queueing delay per request
system.physmem.avgBankLat 12204.10 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30469.54 # Average memory access latency
system.physmem.avgRdBW 15.18 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.18 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 10.19 # Average write queue length over time
system.physmem.readRowHits 429697 # Number of row buffer hits during reads
system.physmem.writeRowHits 77704 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 64.07 # Row buffer hit rate for writes
system.physmem.avgGap 3320924.66 # Average gap between requests
system.l2c.replacements 342985 # number of replacements
system.l2c.tagsinuse 65321.507443 # Cycle average of tags in use
system.l2c.total_refs 2664537 # Total number of references to valid blocks.
system.l2c.sampled_refs 407990 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.530888 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 53803.345548 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4275.017757 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 5362.992247 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 1295.991254 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 584.160637 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.820974 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.065232 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.081833 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.019775 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.008914 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996727 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 631150 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 433289 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 452366 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 409982 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1926787 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 859408 # number of Writeback hits
system.l2c.Writeback_hits::total 859408 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 132 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 86 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 35 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 121498 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 74869 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 196367 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 631150 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 554787 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 452366 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 484851 # number of demand (read+write) hits
system.l2c.demand_hits::total 2123154 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 631150 # number of overall hits
system.l2c.overall_hits::cpu0.data 554787 # number of overall hits
system.l2c.overall_hits::cpu1.inst 452366 # number of overall hits
system.l2c.overall_hits::cpu1.data 484851 # number of overall hits
system.l2c.overall_hits::total 2123154 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 12329 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 272557 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 3043 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1706 # number of ReadReq misses
system.l2c.ReadReq_misses::total 289635 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2549 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 508 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3057 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 48 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 90 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 138 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 103909 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 15834 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 119743 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 12329 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 376466 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3043 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 17540 # number of demand (read+write) misses
system.l2c.demand_misses::total 409378 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 12329 # number of overall misses
system.l2c.overall_misses::cpu0.data 376466 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3043 # number of overall misses
system.l2c.overall_misses::cpu1.data 17540 # number of overall misses
system.l2c.overall_misses::total 409378 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 738936500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 11707644000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 199188500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 90303499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 12736072499 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 388500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 888500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1277000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 198500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 312500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 7293917000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1622405000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 8916322000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 738936500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 19001561000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 199188500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1712708499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 21652394499 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 738936500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 19001561000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 199188500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1712708499 # number of overall miss cycles
system.l2c.overall_miss_latency::total 21652394499 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 643479 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 705846 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 455409 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 411688 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2216422 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 859408 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 859408 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2681 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 594 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3275 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 125 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 206 # number of SCUpgradeReq accesses(hits+misses)
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system.iocache.blocked_cycles::no_mshrs 193065 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23193 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.324279 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41523 # number of writebacks
system.iocache.writebacks::total 41523 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7361197521 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7361197521 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 7373313521 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7373313521 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 7373313521 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7373313521 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177156.274572 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 177156.274572 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176699.422953 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176699.422953 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 7007258 # DTB read hits
system.cpu0.dtb.read_misses 29214 # DTB read misses
system.cpu0.dtb.read_acv 555 # DTB read access violations
system.cpu0.dtb.read_accesses 627494 # DTB read accesses
system.cpu0.dtb.write_hits 4619142 # DTB write hits
system.cpu0.dtb.write_misses 6985 # DTB write misses
system.cpu0.dtb.write_acv 345 # DTB write access violations
system.cpu0.dtb.write_accesses 208744 # DTB write accesses
system.cpu0.dtb.data_hits 11626400 # DTB hits
system.cpu0.dtb.data_misses 36199 # DTB misses
system.cpu0.dtb.data_acv 900 # DTB access violations
system.cpu0.dtb.data_accesses 836238 # DTB accesses
system.cpu0.itb.fetch_hits 888386 # ITB hits
system.cpu0.itb.fetch_misses 27286 # ITB misses
system.cpu0.itb.fetch_acv 998 # ITB acv
system.cpu0.itb.fetch_accesses 915672 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 83155415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 9804849 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 8272695 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 286303 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 6905955 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 4307856 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 619842 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 27789 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 19011041 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 50915714 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 9804849 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 4927698 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 9659436 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1473505 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 28455218 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 29555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 194299 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 211367 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 6349535 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 190370 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 58504859 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.870282 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.201063 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 48845423 83.49% 83.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 638375 1.09% 84.58% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1232766 2.11% 86.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 545499 0.93% 87.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2228588 3.81% 91.43% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 432839 0.74% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 448017 0.77% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 658155 1.12% 94.06% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3475197 5.94% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 58504859 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.117910 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.612296 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 20221803 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 27858596 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8736076 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 771700 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 916683 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 397847 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 27467 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 49800366 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 84499 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 916683 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 21025049 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 10730618 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 14396247 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 8233599 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3202661 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 46975607 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 6729 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 282251 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1314603 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 31610949 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 57450568 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 57189305 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 261263 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 27436892 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4174049 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1166690 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 177857 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 8656888 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 7389019 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 4877617 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 925746 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 640404 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 41641305 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1430691 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 40525941 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 100515 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 4996937 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 2778091 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 970759 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 58504859 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.692694 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.328093 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 40198625 68.71% 68.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 8496961 14.52% 83.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3824833 6.54% 89.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2421122 4.14% 93.91% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1801555 3.08% 96.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 974491 1.67% 98.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 509636 0.87% 99.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 241631 0.41% 99.94% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 36005 0.06% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 58504859 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 54985 10.35% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 255079 48.00% 58.35% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 221355 41.65% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 27833265 68.68% 68.69% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 41848 0.10% 68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 13219 0.03% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 7301690 18.02% 86.85% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 4678009 11.54% 98.39% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 652246 1.61% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 40525941 # Type of FU issued
system.cpu0.iq.rate 0.487352 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 531419 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.013113 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 139814106 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 47896052 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 39650626 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 374568 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 182665 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 177037 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 40857986 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 195589 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 455505 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1004949 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2086 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 10010 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 405892 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 11959 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 139790 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 916683 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 7413565 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 614240 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 45518060 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 556785 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 7389019 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 4877617 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1263664 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 539342 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 5760 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 10010 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 149941 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 281478 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 431419 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 40181745 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 7054742 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 344195 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 2446064 # number of nop insts executed
system.cpu0.iew.exec_refs 11690884 # number of memory reference insts executed
system.cpu0.iew.exec_branches 6330042 # Number of branches executed
system.cpu0.iew.exec_stores 4636142 # Number of stores executed
system.cpu0.iew.exec_rate 0.483213 # Inst execution rate
system.cpu0.iew.wb_sent 39909560 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 39827663 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 19855593 # num instructions producing a value
system.cpu0.iew.wb_consumers 26361633 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.478955 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.753200 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 5375485 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 459932 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 404147 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 57588176 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.695477 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.605159 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 42371011 73.58% 73.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6488229 11.27% 84.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3374360 5.86% 90.70% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1907115 3.31% 94.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1044719 1.81% 95.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 416558 0.72% 96.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 355194 0.62% 97.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 347785 0.60% 97.77% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1283205 2.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 57588176 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 40051259 # Number of instructions committed
system.cpu0.commit.committedOps 40051259 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 10855795 # Number of memory references committed
system.cpu0.commit.loads 6384070 # Number of loads committed
system.cpu0.commit.membars 151085 # Number of memory barriers committed
system.cpu0.commit.branches 6007416 # Number of branches committed
system.cpu0.commit.fp_insts 174841 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 37190024 # Number of committed integer instructions.
system.cpu0.commit.function_calls 489523 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1283205 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 101537476 # The number of ROB reads
system.cpu0.rob.rob_writes 91770556 # The number of ROB writes
system.cpu0.timesIdled 793139 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 24650556 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3710654942 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 37835874 # Number of Instructions Simulated
system.cpu0.committedOps 37835874 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 37835874 # Number of Instructions Simulated
system.cpu0.cpi 2.197793 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.197793 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.455002 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.455002 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 52969279 # number of integer regfile reads
system.cpu0.int_regfile_writes 28937240 # number of integer regfile writes
system.cpu0.fp_regfile_reads 87038 # number of floating regfile reads
system.cpu0.fp_regfile_writes 87248 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1306578 # number of misc regfile reads
system.cpu0.misc_regfile_writes 663412 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 642913 # number of replacements
system.cpu0.icache.tagsinuse 510.325206 # Cycle average of tags in use
system.cpu0.icache.total_refs 5670885 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 643421 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.813646 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 510.325206 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.996729 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.996729 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5670885 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5670885 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5670885 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5670885 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5670885 # number of overall hits
system.cpu0.icache.overall_hits::total 5670885 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 678650 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 678650 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 678650 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 678650 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 678650 # number of overall misses
system.cpu0.icache.overall_misses::total 678650 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9582412994 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 9582412994 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 9582412994 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 9582412994 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 9582412994 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 9582412994 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 6349535 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6349535 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6349535 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 6349535 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 6349535 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 6349535 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.106882 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.106882 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.106882 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.106882 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.106882 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.106882 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14119.815802 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14119.815802 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14119.815802 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14119.815802 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14119.815802 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 2234 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.406897 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 35068 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 35068 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 35068 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 35068 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 35068 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 35068 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 643582 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 643582 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 643582 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 643582 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 643582 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 643582 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7877266496 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7877266496 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7877266496 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 7877266496 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7877266496 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 7877266496 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101359 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.101359 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101359 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.101359 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12239.724691 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12239.724691 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12239.724691 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 932591 # number of replacements
system.cpu0.dcache.tagsinuse 478.331784 # Cycle average of tags in use
system.cpu0.dcache.total_refs 8251917 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 933103 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 8.843522 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 478.331784 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.934242 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.934242 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5164945 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5164945 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 2787881 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 2787881 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136688 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 136688 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 157014 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 157014 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7952826 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 7952826 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7952826 # number of overall hits
system.cpu0.dcache.overall_hits::total 7952826 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1127907 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1127907 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1514074 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1514074 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12708 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 12708 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 640 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2641981 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2641981 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2641981 # number of overall misses
system.cpu0.dcache.overall_misses::total 2641981 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26996447000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 26996447000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62901501244 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 62901501244 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 187201000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 187201000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3956000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 3956000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 89897948244 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 89897948244 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 89897948244 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 89897948244 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6292852 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6292852 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4301955 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4301955 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 149396 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 149396 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157654 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 157654 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 10594807 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 10594807 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 10594807 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 10594807 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.179236 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.179236 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.351950 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.351950 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085063 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085063 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004060 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004060 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249366 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.249366 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249366 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.249366 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23934.993754 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 23934.993754 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41544.535633 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 41544.535633 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.956878 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.956878 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6181.250000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6181.250000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 34026.720194 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34026.720194 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 34026.720194 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2213633 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 2219 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 43644 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.720214 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 317 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 453711 # number of writebacks
system.cpu0.dcache.writebacks::total 453711 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 427154 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 427154 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1285155 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1285155 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3146 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3146 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1712309 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1712309 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1712309 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1712309 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 700753 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 700753 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 228919 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 228919 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9562 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9562 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 640 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 929672 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 929672 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 929672 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 929672 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 17299108000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 17299108000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9077949457 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9077949457 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117930500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117930500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2676000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2676000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26377057457 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 26377057457 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26377057457 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 26377057457 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998607000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998607000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1686748998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1686748998 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2685355998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2685355998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111357 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111357 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053213 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053213 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064004 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064004 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004060 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004060 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.087748 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087748 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.087748 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24686.455855 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24686.455855 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39655.727384 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39655.727384 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12333.246183 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12333.246183 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4181.250000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4181.250000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28372.433995 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28372.433995 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 3713266 # DTB read hits
system.cpu1.dtb.read_misses 14359 # DTB read misses
system.cpu1.dtb.read_acv 33 # DTB read access violations
system.cpu1.dtb.read_accesses 328215 # DTB read accesses
system.cpu1.dtb.write_hits 2351870 # DTB write hits
system.cpu1.dtb.write_misses 2326 # DTB write misses
system.cpu1.dtb.write_acv 62 # DTB write access violations
system.cpu1.dtb.write_accesses 130566 # DTB write accesses
system.cpu1.dtb.data_hits 6065136 # DTB hits
system.cpu1.dtb.data_misses 16685 # DTB misses
system.cpu1.dtb.data_acv 95 # DTB access violations
system.cpu1.dtb.data_accesses 458781 # DTB accesses
system.cpu1.itb.fetch_hits 552396 # ITB hits
system.cpu1.itb.fetch_misses 7861 # ITB misses
system.cpu1.itb.fetch_acv 226 # ITB acv
system.cpu1.itb.fetch_accesses 560257 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 34615367 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 5312293 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 4360790 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 184753 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 3627578 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 1933378 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 383381 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 19114 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 12153279 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 25592027 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 5312293 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 2316759 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 4666723 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 848042 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 13957627 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 25440 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 65073 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 147747 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 2992364 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 115997 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 31571084 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.810616 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.170872 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 26904361 85.22% 85.22% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 276998 0.88% 86.10% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 593564 1.88% 87.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 353090 1.12% 89.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 710175 2.25% 91.34% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 234476 0.74% 92.09% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 277213 0.88% 92.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 377383 1.20% 94.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1843824 5.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 31571084 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.153466 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.739326 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 12173556 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 14265063 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 4322746 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 271541 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 538177 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 245868 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 17179 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 25069869 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 51217 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 538177 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 12622413 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 4307697 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 8552551 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 4022106 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 1528138 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 23469307 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 403073 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 318746 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 15460907 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 27951432 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 27722595 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 228837 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 13017644 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2443263 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 711049 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 79879 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 4546986 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 3946391 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 2480141 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 398992 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 247125 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 20556503 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 873226 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 19920635 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 45889 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 3011838 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 1481780 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 622079 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 31571084 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.630977 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.308978 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 22947759 72.69% 72.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 3816292 12.09% 84.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1671768 5.30% 90.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 1218822 3.86% 93.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 1072376 3.40% 97.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 425454 1.35% 98.67% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 262904 0.83% 99.51% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 135529 0.43% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 20180 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 31571084 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 28274 8.56% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 166109 50.30% 58.86% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 135868 41.14% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 13189448 66.21% 66.23% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 28632 0.14% 66.37% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.37% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 12556 0.06% 66.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 3884810 19.50% 85.94% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 2385812 11.98% 97.92% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 414088 2.08% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 19920635 # Type of FU issued
system.cpu1.iq.rate 0.575485 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 330251 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.016578 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 71458593 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 24286363 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 19388343 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 329901 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 159417 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 155652 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 20074577 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 172783 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 184439 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 581301 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 1183 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 4340 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 230089 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 6918 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 18073 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 538177 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 3253999 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 229517 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 22699099 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 268114 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 3946391 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 2480141 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 779721 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 89744 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2529 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 4340 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 96593 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 181110 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 277703 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 19708494 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 3738657 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 212141 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 1269370 # number of nop insts executed
system.cpu1.iew.exec_refs 6100523 # number of memory reference insts executed
system.cpu1.iew.exec_branches 3128191 # Number of branches executed
system.cpu1.iew.exec_stores 2361866 # Number of stores executed
system.cpu1.iew.exec_rate 0.569357 # Inst execution rate
system.cpu1.iew.wb_sent 19587937 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 19543995 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 9462232 # num instructions producing a value
system.cpu1.iew.wb_consumers 13383566 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.564605 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.707004 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 3264810 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 251147 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 260251 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 31032907 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.624350 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.557822 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 23883562 76.96% 76.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 2995086 9.65% 86.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 1581522 5.10% 91.71% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 799862 2.58% 94.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 502768 1.62% 95.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 236983 0.76% 96.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 224339 0.72% 97.39% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 194617 0.63% 98.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 614168 1.98% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 31032907 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 19375400 # Number of instructions committed
system.cpu1.commit.committedOps 19375400 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 5615142 # Number of memory references committed
system.cpu1.commit.loads 3365090 # Number of loads committed
system.cpu1.commit.membars 85627 # Number of memory barriers committed
system.cpu1.commit.branches 2912516 # Number of branches committed
system.cpu1.commit.fp_insts 154287 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 17850043 # Number of committed integer instructions.
system.cpu1.commit.function_calls 300496 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 614168 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 52972716 # The number of ROB reads
system.cpu1.rob.rob_writes 45818344 # The number of ROB writes
system.cpu1.timesIdled 377037 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 3044283 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3758611040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 18256718 # Number of Instructions Simulated
system.cpu1.committedOps 18256718 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 18256718 # Number of Instructions Simulated
system.cpu1.cpi 1.896034 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.896034 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.527417 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.527417 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 25482349 # number of integer regfile reads
system.cpu1.int_regfile_writes 13944369 # number of integer regfile writes
system.cpu1.fp_regfile_reads 81651 # number of floating regfile reads
system.cpu1.fp_regfile_writes 82372 # number of floating regfile writes
system.cpu1.misc_regfile_reads 840995 # number of misc regfile reads
system.cpu1.misc_regfile_writes 357443 # number of misc regfile writes
system.cpu1.icache.replacements 454861 # number of replacements
system.cpu1.icache.tagsinuse 506.121737 # Cycle average of tags in use
system.cpu1.icache.total_refs 2515591 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 455373 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 5.524243 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 42848278000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 506.121737 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.988519 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.988519 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 2515591 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 2515591 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 2515591 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 2515591 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 2515591 # number of overall hits
system.cpu1.icache.overall_hits::total 2515591 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 476773 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 476773 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 476773 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 476773 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 476773 # number of overall misses
system.cpu1.icache.overall_misses::total 476773 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6462749000 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 6462749000 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 6462749000 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 6462749000 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 6462749000 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 6462749000 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 2992364 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 2992364 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 2992364 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 2992364 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 2992364 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2992364 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.159330 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.159330 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.159330 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.159330 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.159330 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.159330 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13555.190835 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13555.190835 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13555.190835 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13555.190835 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13555.190835 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 884 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.808511 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21323 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 21323 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 21323 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 21323 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 21323 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 21323 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 455450 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 455450 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 455450 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 455450 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 455450 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 455450 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5356907000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5356907000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5356907000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5356907000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5356907000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5356907000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.152204 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.152204 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152204 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.152204 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11761.789439 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11761.789439 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11761.789439 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 520860 # number of replacements
system.cpu1.dcache.tagsinuse 498.284346 # Cycle average of tags in use
system.cpu1.dcache.total_refs 4488456 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 521257 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 8.610831 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 31290571500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 498.284346 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.973212 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.973212 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 2711578 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2711578 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1652227 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1652227 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59380 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 59380 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 66046 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 66046 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 4363805 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 4363805 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 4363805 # number of overall hits
system.cpu1.dcache.overall_hits::total 4363805 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 735473 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 735473 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 523667 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 523667 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12800 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 12800 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 689 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 689 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 1259140 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 1259140 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 1259140 # number of overall misses
system.cpu1.dcache.overall_misses::total 1259140 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 11275775500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 11275775500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16995132775 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 16995132775 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 186282500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 186282500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5003500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 5003500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 28270908275 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 28270908275 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 28270908275 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 28270908275 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3447051 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 3447051 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2175894 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 2175894 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72180 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 72180 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 66735 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 66735 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 5622945 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 5622945 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 5622945 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 5622945 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.213363 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.213363 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.240668 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.240668 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177334 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177334 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.010324 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.010324 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.223929 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.223929 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.223929 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.223929 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15331.324875 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15331.324875 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32454.083941 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32454.083941 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14553.320312 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14553.320312 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7261.973875 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7261.973875 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22452.553548 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22452.553548 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 22452.553548 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 551348 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 10411 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 52.958217 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 405697 # number of writebacks
system.cpu1.dcache.writebacks::total 405697 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 310580 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 310580 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 431476 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 431476 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2432 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2432 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 742056 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 742056 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 742056 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 742056 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 424893 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 424893 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92191 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 92191 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 10368 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10368 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 689 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 689 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 517084 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 517084 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 517084 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 517084 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5584148500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5584148500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2607634127 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2607634127 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126008000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126008000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3625500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3625500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8191782627 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 8191782627 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8191782627 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 8191782627 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485715000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485715000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 920480500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 920480500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1406195500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1406195500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.123263 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.123263 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042369 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042369 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.143641 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.143641 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.010324 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.010324 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.091960 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.091960 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.091960 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13142.481754 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13142.481754 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28285.126824 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28285.126824 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12153.549383 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12153.549383 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5261.973875 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5261.973875 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15842.266686 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15842.266686 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 4859 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 144961 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 48033 39.13% 39.13% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 133 0.11% 39.24% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1924 1.57% 40.81% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 16 0.01% 40.82% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 72639 59.18% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 122745 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 47372 48.94% 48.94% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 133 0.14% 49.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1924 1.99% 51.06% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 16 0.02% 51.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 47357 48.92% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 96802 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1866486525500 98.40% 98.40% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 63938000 0.00% 98.40% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 572947000 0.03% 98.43% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 8827500 0.00% 98.43% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 29774513500 1.57% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1896906751500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.986239 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.651950 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.788643 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed
system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed
system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 211 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 97 0.07% 0.08% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed
system.cpu0.kern.callpal::swpctx 2435 1.87% 1.95% # number of callpals executed
system.cpu0.kern.callpal::tbi 48 0.04% 1.98% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.01% 1.99% # number of callpals executed
system.cpu0.kern.callpal::swpipl 116655 89.61% 91.60% # number of callpals executed
system.cpu0.kern.callpal::rdps 6417 4.93% 96.53% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.53% # number of callpals executed
system.cpu0.kern.callpal::wrusp 4 0.00% 96.54% # number of callpals executed
system.cpu0.kern.callpal::rdusp 8 0.01% 96.54% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.54% # number of callpals executed
system.cpu0.kern.callpal::rti 4017 3.09% 99.63% # number of callpals executed
system.cpu0.kern.callpal::callsys 345 0.27% 99.89% # number of callpals executed
system.cpu0.kern.callpal::imb 137 0.11% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 130177 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5807 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1286
system.cpu0.kern.mode_good::user 1287
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.221457 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.362701 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1894993254500 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1913489000 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 2436 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 3786 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 92502 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 33560 40.13% 40.13% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1921 2.30% 42.42% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 97 0.12% 42.54% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 48058 57.46% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 83636 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 32844 48.58% 48.58% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1921 2.84% 51.42% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 97 0.14% 51.56% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 32747 48.44% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 67609 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1867334401000 98.46% 98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 533283000 0.03% 98.48% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 45472500 0.00% 98.49% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 28701925000 1.51% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1896615081500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.978665 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.681406 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.808372 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 115 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1813 2.11% 2.13% # number of callpals executed
system.cpu1.kern.callpal::tbi 6 0.01% 2.14% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed
system.cpu1.kern.callpal::swpipl 78432 91.18% 93.32% # number of callpals executed
system.cpu1.kern.callpal::rdps 2336 2.72% 96.04% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 96.04% # number of callpals executed
system.cpu1.kern.callpal::wrusp 3 0.00% 96.04% # number of callpals executed
system.cpu1.kern.callpal::rdusp 1 0.00% 96.04% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 96.05% # number of callpals executed
system.cpu1.kern.callpal::rti 3185 3.70% 99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys 172 0.20% 99.95% # number of callpals executed
system.cpu1.kern.callpal::imb 43 0.05% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 86022 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2264 # number of protection mode switches
system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 518
system.cpu1.kern.mode_good::user 459
system.cpu1.kern.mode_good::idle 59
system.cpu1.kern.mode_switch_good::kernel 0.228799 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.028964 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.217647 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 42822911000 2.26% 2.26% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 817792500 0.04% 2.30% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1852963538500 97.70% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1814 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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