76cd4393c0
Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.
* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).
* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.
* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
348 lines
11 KiB
C++
348 lines
11 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "base/bitfield.hh"
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#include "debug/I8259.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8259.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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X86ISA::I8259::I8259(Params * p)
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: BasicPioDevice(p, 2), IntDevice(this),
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latency(p->pio_latency), output(p->output),
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mode(p->mode), slave(p->slave),
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IRR(0), ISR(0), IMR(0),
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readIRR(true), initControlWord(0), autoEOI(false)
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{
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for (int i = 0; i < NumLines; i++)
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pinStates[i] = false;
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}
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Tick
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X86ISA::I8259::read(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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switch(pkt->getAddr() - pioAddr)
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{
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case 0x0:
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if (readIRR) {
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DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
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pkt->set(IRR);
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} else {
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DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
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pkt->set(ISR);
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}
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break;
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case 0x1:
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DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
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pkt->set(IMR);
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break;
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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Tick
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X86ISA::I8259::write(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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uint8_t val = pkt->get<uint8_t>();
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switch (pkt->getAddr() - pioAddr) {
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case 0x0:
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if (bits(val, 4)) {
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DPRINTF(I8259, "Received initialization command word 1.\n");
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IMR = 0;
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edgeTriggered = bits(val, 3);
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DPRINTF(I8259, "%s triggered mode.\n",
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edgeTriggered ? "Edge" : "Level");
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cascadeMode = !bits(val, 1);
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DPRINTF(I8259, "%s mode.\n",
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cascadeMode ? "Cascade" : "Single");
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expectICW4 = bits(val, 0);
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if (!expectICW4) {
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autoEOI = false;
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}
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initControlWord = 1;
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DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
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} else if (bits(val, 4, 3) == 0) {
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DPRINTF(I8259, "Received operation command word 2.\n");
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switch (bits(val, 7, 5)) {
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case 0x0:
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DPRINTF(I8259,
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"Subcommand: Rotate in auto-EOI mode (clear).\n");
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break;
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case 0x1:
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{
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int line = findMsbSet(ISR);
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DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
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line);
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handleEOI(line);
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}
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break;
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case 0x2:
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DPRINTF(I8259, "Subcommand: No operation.\n");
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break;
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case 0x3:
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{
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int line = bits(val, 2, 0);
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DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
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line);
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handleEOI(line);
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}
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break;
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case 0x4:
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DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
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break;
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case 0x5:
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DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
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break;
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case 0x6:
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DPRINTF(I8259, "Subcommand: Set priority command.\n");
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DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
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bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
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break;
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case 0x7:
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DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
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DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n",
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bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
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break;
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}
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} else if (bits(val, 4, 3) == 1) {
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DPRINTF(I8259, "Received operation command word 3.\n");
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if (bits(val, 7)) {
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DPRINTF(I8259, "%s special mask mode.\n",
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bits(val, 6) ? "Set" : "Clear");
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}
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if (bits(val, 1)) {
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readIRR = bits(val, 0);
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DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
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}
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}
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break;
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case 0x1:
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switch (initControlWord) {
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case 0x0:
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DPRINTF(I8259, "Received operation command word 1.\n");
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DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
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IMR = val;
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break;
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case 0x1:
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DPRINTF(I8259, "Received initialization command word 2.\n");
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vectorOffset = val & ~mask(3);
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DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
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vectorOffset, vectorOffset | mask(3));
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if (cascadeMode) {
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initControlWord++;
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} else {
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cascadeBits = 0;
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initControlWord = 0;
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}
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break;
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case 0x2:
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DPRINTF(I8259, "Received initialization command word 3.\n");
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if (mode == Enums::I8259Master) {
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DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
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bits(val, 0) ? " 0" : "",
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bits(val, 1) ? " 1" : "",
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bits(val, 2) ? " 2" : "",
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bits(val, 3) ? " 3" : "",
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bits(val, 4) ? " 4" : "",
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bits(val, 5) ? " 5" : "",
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bits(val, 6) ? " 6" : "",
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bits(val, 7) ? " 7" : "");
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cascadeBits = val;
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} else {
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DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
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cascadeBits = val & mask(3);
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}
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if (expectICW4)
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initControlWord++;
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else
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initControlWord = 0;
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break;
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case 0x3:
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DPRINTF(I8259, "Received initialization command word 4.\n");
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if (bits(val, 4)) {
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DPRINTF(I8259, "Special fully nested mode.\n");
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} else {
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DPRINTF(I8259, "Not special fully nested mode.\n");
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}
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if (bits(val, 3) == 0) {
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DPRINTF(I8259, "Nonbuffered.\n");
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} else if (bits(val, 2) == 0) {
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DPRINTF(I8259, "Buffered.\n");
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} else {
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DPRINTF(I8259, "Unrecognized buffer mode.\n");
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}
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autoEOI = bits(val, 1);
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DPRINTF(I8259, "%s End Of Interrupt.\n",
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autoEOI ? "Automatic" : "Normal");
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DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
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initControlWord = 0;
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break;
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}
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break;
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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void
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X86ISA::I8259::handleEOI(int line)
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{
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ISR &= ~(1 << line);
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// There may be an interrupt that was waiting which can
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// now be sent.
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if (IRR)
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requestInterrupt(findMsbSet(IRR));
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}
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void
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X86ISA::I8259::requestInterrupt(int line)
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{
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if (bits(ISR, 7, line) == 0) {
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if (output) {
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DPRINTF(I8259, "Propogating interrupt.\n");
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output->raise();
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//XXX This is a hack.
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output->lower();
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} else {
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warn("Received interrupt but didn't have "
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"anyone to tell about it.\n");
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}
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}
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}
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void
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X86ISA::I8259::signalInterrupt(int line)
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{
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DPRINTF(I8259, "Interrupt requested for line %d.\n", line);
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if (line >= NumLines)
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fatal("Line number %d doesn't exist. The max is %d.\n",
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line, NumLines - 1);
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if (bits(IMR, line)) {
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DPRINTF(I8259, "Interrupt %d was masked.\n", line);
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} else {
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IRR |= 1 << line;
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requestInterrupt(line);
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}
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}
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void
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X86ISA::I8259::raiseInterruptPin(int number)
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{
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DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number);
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if (number >= NumLines)
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fatal("Line number %d doesn't exist. The max is %d.\n",
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number, NumLines - 1);
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if (!pinStates[number])
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signalInterrupt(number);
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pinStates[number] = true;
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}
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void
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X86ISA::I8259::lowerInterruptPin(int number)
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{
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DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number);
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if (number >= NumLines)
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fatal("Line number %d doesn't exist. The max is %d.\n",
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number, NumLines - 1);
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pinStates[number] = false;
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}
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int
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X86ISA::I8259::getVector()
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{
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/*
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* This code only handles one slave. Since that's how the PC platform
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* always uses the 8259 PIC, there shouldn't be any need for more. If
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* there -is- a need for more for some reason, "slave" can become a
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* vector of slaves.
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*/
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int line = findMsbSet(IRR);
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IRR &= ~(1 << line);
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DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
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if (autoEOI) {
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handleEOI(line);
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} else {
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ISR |= 1 << line;
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}
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if (slave && bits(cascadeBits, line)) {
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DPRINTF(I8259, "Interrupt was from slave who will "
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"provide the vector.\n");
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return slave->getVector();
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}
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return line | vectorOffset;
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}
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void
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X86ISA::I8259::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_ARRAY(pinStates, NumLines);
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SERIALIZE_ENUM(mode);
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SERIALIZE_SCALAR(IRR);
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SERIALIZE_SCALAR(ISR);
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SERIALIZE_SCALAR(IMR);
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SERIALIZE_SCALAR(vectorOffset);
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SERIALIZE_SCALAR(cascadeMode);
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SERIALIZE_SCALAR(cascadeBits);
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SERIALIZE_SCALAR(edgeTriggered);
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SERIALIZE_SCALAR(readIRR);
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SERIALIZE_SCALAR(expectICW4);
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SERIALIZE_SCALAR(initControlWord);
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SERIALIZE_SCALAR(autoEOI);
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}
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void
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X86ISA::I8259::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_ARRAY(pinStates, NumLines);
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UNSERIALIZE_ENUM(mode);
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UNSERIALIZE_SCALAR(IRR);
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UNSERIALIZE_SCALAR(ISR);
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UNSERIALIZE_SCALAR(IMR);
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UNSERIALIZE_SCALAR(vectorOffset);
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UNSERIALIZE_SCALAR(cascadeMode);
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UNSERIALIZE_SCALAR(cascadeBits);
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UNSERIALIZE_SCALAR(edgeTriggered);
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UNSERIALIZE_SCALAR(readIRR);
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UNSERIALIZE_SCALAR(expectICW4);
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UNSERIALIZE_SCALAR(initControlWord);
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UNSERIALIZE_SCALAR(autoEOI);
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}
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X86ISA::I8259 *
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I8259Params::create()
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{
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return new X86ISA::I8259(this);
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}
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