139c97c977
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing devices to use the new header location. This also renames the PCIDEV debug flag to have a capitalization that is consistent with the PCI host and other devices. --HG-- rename : src/dev/Pci.py => src/dev/pci/PciDevice.py rename : src/dev/pcidev.cc => src/dev/pci/device.cc rename : src/dev/pcidev.hh => src/dev/pci/device.hh rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
409 lines
15 KiB
C
409 lines
15 KiB
C
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Miguel Serrano
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*/
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/* @file
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* Device register definitions for a device's PCI config space
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*/
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#ifndef __PCIREG_H__
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#define __PCIREG_H__
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#include <sys/types.h>
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#include "base/bitfield.hh"
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#include "base/bitunion.hh"
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union PCIConfig {
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uint8_t data[64];
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struct {
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uint16_t vendor;
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uint16_t device;
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uint16_t command;
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uint16_t status;
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uint8_t revision;
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uint8_t progIF;
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uint8_t subClassCode;
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uint8_t classCode;
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uint8_t cacheLineSize;
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uint8_t latencyTimer;
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uint8_t headerType;
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uint8_t bist;
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uint32_t baseAddr[6];
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uint32_t cardbusCIS;
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uint16_t subsystemVendorID;
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uint16_t subsystemID;
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uint32_t expansionROM;
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uint8_t capabilityPtr;
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// Was 8 bytes in the legacy PCI spec, but to support PCIe
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// this field is now 7 bytes with PCIe's addition of the
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// capability list pointer.
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uint8_t reserved[7];
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uint8_t interruptLine;
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uint8_t interruptPin;
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uint8_t minimumGrant;
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uint8_t maximumLatency;
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};
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};
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// Common PCI offsets
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#define PCI_VENDOR_ID 0x00 // Vendor ID ro
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#define PCI_DEVICE_ID 0x02 // Device ID ro
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#define PCI_COMMAND 0x04 // Command rw
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#define PCI_STATUS 0x06 // Status rw
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#define PCI_REVISION_ID 0x08 // Revision ID ro
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#define PCI_CLASS_CODE 0x09 // Class Code ro
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#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
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#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
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#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
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#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
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#define PCI_HEADER_TYPE 0x0E // Header Type ro
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#define PCI_BIST 0x0F // Built in self test rw
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// some pci command reg bitfields
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#define PCI_CMD_BME 0x04 // Bus master function enable
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#define PCI_CMD_MSE 0x02 // Memory Space Access enable
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#define PCI_CMD_IOSE 0x01 // I/O space enable
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// Type 0 PCI offsets
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#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
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#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
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#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
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#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
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#define PCI0_CIS 0x28 // CardBus CIS Pointer ro
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#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
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#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
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#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
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#define PCI0_CAP_PTR 0x34 // Capability list pointer ro
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#define PCI0_RESERVED 0x35
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#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
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#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
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#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
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#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
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// Type 1 PCI offsets
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#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
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#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
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#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
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#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
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#define PCI1_IO_BASE 0x1C // I/O Base rw
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#define PCI1_IO_LIMIT 0x1D // I/O Limit rw
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#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
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#define PCI1_MEM_BASE 0x20 // Memory Base rw
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#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
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#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
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#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
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#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
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#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
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#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
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#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
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#define PCI1_RESERVED 0x34 // Reserved ro
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#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
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#define PCI1_INTR_LINE 0x3C // Interrupt Line rw
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#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
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#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
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// Device specific offsets
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#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
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#define PCI_CONFIG_SIZE 0xFF
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// Some Vendor IDs
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#define PCI_VENDOR_DEC 0x1011
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#define PCI_VENDOR_NCR 0x101A
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#define PCI_VENDOR_QLOGIC 0x1077
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#define PCI_VENDOR_SIMOS 0x1291
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// Some Product IDs
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#define PCI_PRODUCT_DEC_PZA 0x0008
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#define PCI_PRODUCT_NCR_810 0x0001
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#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
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#define PCI_PRODUCT_SIMOS_SIMOS 0x1291
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#define PCI_PRODUCT_SIMOS_ETHER 0x1292
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/**
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* PCIe capability list offsets internal to the entry.
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* Actual offsets in the PCI config space are defined in
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* the python files setting up the system.
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*/
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#define PMCAP_ID 0x00
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#define PMCAP_PC 0x02
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#define PMCAP_PMCS 0x04
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#define PMCAP_SIZE 0x06
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#define MSICAP_ID 0x00
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#define MSICAP_MC 0x02
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#define MSICAP_MA 0x04
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#define MSICAP_MUA 0x08
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#define MSICAP_MD 0x0C
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#define MSICAP_MMASK 0x10
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#define MSICAP_MPEND 0x14
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#define MSICAP_SIZE 0x18
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#define MSIXCAP_ID 0x00
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#define MSIXCAP_MXC 0x02
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#define MSIXCAP_MTAB 0x04
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#define MSIXCAP_MPBA 0x08
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#define MSIXCAP_SIZE 0x0C
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#define PXCAP_ID 0x00
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#define PXCAP_PXCAP 0x02
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#define PXCAP_PXDCAP 0x04
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#define PXCAP_PXDC 0x08
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#define PXCAP_PXDS 0x0A
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#define PXCAP_PXLCAP 0x0C
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#define PXCAP_PXLC 0x10
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#define PXCAP_PXLS 0x12
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#define PXCAP_PXDCAP2 0x24
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#define PXCAP_PXDC2 0x28
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#define PXCAP_SIZE 0x30
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/** @struct PMCAP
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* Defines the Power Management capability register and all its associated
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* bitfields for a PCIe device.
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*/
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union PMCAP {
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uint8_t data[6];
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struct {
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uint16_t pid; /* 0:7 cid
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* 8:15 next
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*/
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uint16_t pc; /* 0:2 vs
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* 3 pmec
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* 4 reserved
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* 5 dsi
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* 6:8 auxc
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* 9 d1s
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* 10 d2s
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* 11:15 psup
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*/
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uint16_t pmcs; /* 0:1 ps
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* 2 reserved
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* 3 nsfrst
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* 4:7 reserved
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* 8 pmee
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* 9:12 dse
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* 13:14 dsc
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* 15 pmes
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*/
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};
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};
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/** @struct MSICAP
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* Defines the MSI Capability register and its associated bitfields for
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* the a PCI/PCIe device. Both the MSI capability and the MSIX capability
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* can be filled in if a device model supports both, but only 1 of
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* MSI/MSIX/INTx interrupt mode can be selected at a given time.
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*/
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union MSICAP {
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uint8_t data[24];
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struct {
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uint16_t mid; /* 0:7 cid
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* 8:15 next
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*/
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uint16_t mc; /* 0 msie;
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* 1:3 mmc;
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* 4:6 mme;
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* 7 c64;
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* 8 pvm;
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* 9:15 reserved;
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*/
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uint32_t ma; /* 0:1 reserved
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* 2:31 addr
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*/
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uint32_t mua;
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uint16_t md;
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uint32_t mmask;
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uint32_t mpend;
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};
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};
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/** @struct MSIX
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* Defines the MSI-X Capability register and its associated bitfields for
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* a PCIe device.
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*/
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union MSIXCAP {
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uint8_t data[12];
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struct {
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uint16_t mxid; /* 0:7 cid
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* 8:15 next
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*/
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uint16_t mxc; /* 0:10 ts;
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* 11:13 reserved;
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* 14 fm;
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* 15 mxe;
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*/
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uint32_t mtab; /* 0:2 tbir;
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* 3:31 to;
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*/
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uint32_t mpba; /* 0:2 pbir;
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* 3:31> pbao;
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*/
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};
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};
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union MSIXTable {
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struct {
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uint32_t addr_lo;
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uint32_t addr_hi;
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uint32_t msg_data;
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uint32_t vec_ctrl;
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} fields;
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uint32_t data[4];
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};
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#define MSIXVECS_PER_PBA 64
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struct MSIXPbaEntry {
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uint64_t bits;
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};
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/** @struct PXCAP
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* Defines the PCI Express capability register and its associated bitfields
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* for a PCIe device.
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*/
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struct PXCAP {
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uint8_t data[48];
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struct {
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uint16_t pxid; /* 0:7 cid
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* 8:15 next
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*/
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uint16_t pxcap; /* 0:3 ver;
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* 4:7 dpt;
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* 8 si;
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* 9:13 imn;
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* 14:15 reserved;
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*/
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uint32_t pxdcap; /* 0:2 mps;
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* 3:4 pfs;
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* 5 etfs;
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* 6:8 l0sl;
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* 9:11 l1l;
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* 12:14 reserved;
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* 15 rer;
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* 16:17 reserved;
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* 18:25 csplv;
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* 26:27 cspls;
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* 28 flrc;
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* 29:31 reserved;
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*/
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uint16_t pxdc; /* 0 cere;
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* 1 nfere;
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* 2 fere;
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* 3 urre;
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* 4 ero;
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* 5:7 mps;
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* 8 ete;
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* 9 pfe;
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* 10 appme;
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* 11 ens;
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* 12:14 mrrs;
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* 15 func_reset;
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*/
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uint16_t pxds; /* 0 ced;
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* 1 nfed;
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* 2 fed;
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* 3 urd;
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* 4 apd;
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* 5 tp;
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* 6:15 reserved;
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*/
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uint32_t pxlcap; /* 0:3 sls;
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* 4:9 mlw;
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* 10:11 aspms;
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* 12:14 l0sel;
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* 15:17 l1el;
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* 18 cpm;
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* 19 sderc;
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* 20 dllla;
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* 21 lbnc;
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* 22:23 reserved;
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* 24:31 pn;
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*/
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uint16_t pxlc; /* 0:1 aspmc;
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* 2 reserved;
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* 3 rcb;
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* 4:5 reserved;
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* 6 ccc;
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* 7 es;
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* 8 ecpm;
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* 9 hawd;
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* 10:15 reserved;
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*/
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uint16_t pxls; /* 0:3 cls;
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* 4:9 nlw;
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* 10:11 reserved;
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* 12 slot_clk_config;
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* 13:15 reserved;
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*/
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uint8_t reserved[20];
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uint32_t pxdcap2; /* 0:3 ctrs;
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* 4 ctds;
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* 5 arifs;
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* 6 aors;
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* 7 aocs32;
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* 8 aocs64;
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* 9 ccs128;
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* 10 nprpr;
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* 11 ltrs;
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* 12:13 tphcs;
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* 14:17 reserved;
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* 18:19 obffs;
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* 20 effs;
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* 21 eetps;
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* 22:23 meetp;
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* 24:31 reserved;
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*/
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uint32_t pxdc2; /* 0:3 ctv;
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* 4 ctd;
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* 5:9 reserved;
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* 10 ltrme;
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* 11:12 reserved;
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* 13:14 obffe;
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* 15:31 reserved;
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*/
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};
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};
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#endif // __PCIREG_H__
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