3cf24f9716
Connects M5 cpu and dma ports directly to ruby sequencers and dma sequencers. Rubymem also includes a pio port so that pio requests and be forwarded to a special pio bus connecting to device pio ports.
182 lines
5.8 KiB
Python
182 lines
5.8 KiB
Python
# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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#
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# Full system configuraiton for ruby
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#
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import os
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import optparse
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import sys
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from os.path import join as joinpath
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, panic
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if not buildEnv['FULL_SYSTEM']:
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panic("This script requires full-system mode (*_FS).")
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addToPath('../../tests/configs/')
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addToPath('../common')
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import ruby_config
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Simulation
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from Caches import *
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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# Benchmark options
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parser.add_option("-b", "--benchmark", action="store", type="string",
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dest="benchmark",
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help="Specify the benchmark to run. Available benchmarks: %s"\
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% DefinedBenchmarks)
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parser.add_option("-o", "--options", default="",
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help='The options to pass to the binary, use " " around the entire string')
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parser.add_option("-i", "--input", default="", help="Read stdin from a file.")
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parser.add_option("--output", default="", help="Redirect stdout to a file.")
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parser.add_option("--errout", default="", help="Redirect stderr to a file.")
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parser.add_option("--ruby-debug", action="store_true")
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parser.add_option("--ruby-debug-file", default="", help="Ruby debug out file (stdout if blank)")
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# ruby host memory experimentation
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parser.add_option("--cache_size", type="int")
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parser.add_option("--cache_assoc", type="int")
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parser.add_option("--map_levels", type="int")
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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bm = [SysConfig()]
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#
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# currently ruby fs only works in timing mode because ruby does not support
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# atomic accesses by devices
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#
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assert(options.timing)
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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CPUClass.clock = '1GHz'
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#
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# Since we are running in timing mode, set the number of M5 ticks to ruby ticks
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# to the cpu clock frequency
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#
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M5_to_ruby_tick = '1000t'
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np = options.num_cpus
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# check for max instruction count
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if options.max_inst:
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max_inst = options.max_inst
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else:
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max_inst = 0
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# set cache size
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if options.cache_size:
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cache_size = options.cache_size
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else:
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cache_size = 32768 # 32 kB is default
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# set cache assoc
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if options.cache_assoc:
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cache_assoc = options.cache_assoc
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else:
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cache_assoc = 8 # 8 is default
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# set map levels
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if options.map_levels:
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map_levels = options.map_levels
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else:
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map_levels = 4 # 4 levels is the default
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#
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# Currently, since ruby configuraiton is separate from m5, we need to manually
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# tell ruby that two dma ports are created by makeLinuxAlphaRubySystem().
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# Eventually, this will be fix with a unified configuration system.
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#
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rubymem = ruby_config.generate("MI_example-homogeneous.rb",
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np,
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np,
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128,
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False,
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cache_size,
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cache_assoc,
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map_levels,
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2,
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M5_to_ruby_tick)
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if options.ruby_debug == True:
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rubymem.debug = True
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rubymem.debug_file = options.ruby_debug_file
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system = makeLinuxAlphaRubySystem(test_mem_mode, rubymem, bm[0])
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(np)]
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if options.l2cache:
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print "Error: -l2cache incompatible with ruby, must configure it ruby-style"
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sys.exit(1)
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if options.caches:
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print "Error: -caches incompatible with ruby, must configure it ruby-style"
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sys.exit(1)
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for i in xrange(np):
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system.cpu[i].connectMemPorts(system.physmem)
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if options.fastmem:
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system.cpu[i].physmem_port = system.physmem.port
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root = Root(system = system)
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Simulation.run(options, root, system, FutureClass)
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