dccca0d3a9
This patch introduces port access methods that separates snoop request/responses from normal memory request/responses. The differentiation is made for functional, atomic and timing accesses and builds on the introduction of master and slave ports. Before the introduction of this patch, the packets belonging to the different phases of the protocol (request -> [forwarded snoop request -> snoop response]* -> response) all use the same port access functions, even though the snoop packets flow in the opposite direction to the normal packet. That is, a coherent master sends normal request and receives responses, but receives snoop requests and sends snoop responses (vice versa for the slave). These two distinct phases now use different access functions, as described below. Starting with the functional access, a master sends a request to a slave through sendFunctional, and the request packet is turned into a response before the call returns. In a system without cache coherence, this is all that is needed from the functional interface. For the cache-coherent scenario, a slave also sends snoop requests to coherent masters through sendFunctionalSnoop, with responses returned within the same packet pointer. This is currently used by the bus and caches, and the LSQ of the O3 CPU. The send/recvFunctional and send/recvFunctionalSnoop are moved from the Port super class to the appropriate subclass. Atomic accesses follow the same flow as functional accesses, with request being sent from master to slave through sendAtomic. In the case of cache-coherent ports, a slave can send snoop requests to a master through sendAtomicSnoop. Just as for the functional access methods, the atomic send and receive member functions are moved to the appropriate subclasses. The timing access methods are different from the functional and atomic in that requests and responses are separated in time and send/recvTiming are used for both directions. Hence, a master uses sendTiming to send a request to a slave, and a slave uses sendTiming to send a response back to a master, at a later point in time. Snoop requests and responses travel in the opposite direction, similar to what happens in functional and atomic accesses. With the introduction of this patch, it is possible to determine the direction of packets in the bus, and no longer necessary to look for both a master and a slave port with the requested port id. In contrast to the normal recvFunctional, recvAtomic and recvTiming that are pure virtual functions, the recvFunctionalSnoop, recvAtomicSnoop and recvTimingSnoop have a default implementation that calls panic. This is to allow non-coherent master and slave ports to not implement these functions.
964 lines
27 KiB
C++
964 lines
27 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#include "arch/locked_mem.hh"
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#include "arch/mmapped_ipr.hh"
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "config/the_isa.hh"
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#include "cpu/simple/timing.hh"
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#include "cpu/exetrace.hh"
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#include "debug/Config.hh"
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "params/TimingSimpleCPU.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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void
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TimingSimpleCPU::init()
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{
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BaseCPU::init();
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// Initialise the ThreadContext's memory proxies
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tcBase()->initMemProxies(tcBase());
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if (FullSystem) {
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(tc, _cpuId);
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}
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}
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}
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void
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TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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{
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pkt = _pkt;
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cpu->schedule(this, t);
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}
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TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
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: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
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dcachePort(this), fetchEvent(this)
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{
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_status = Idle;
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ifetch_pkt = dcache_pkt = NULL;
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drainEvent = NULL;
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previousTick = 0;
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changeState(SimObject::Running);
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system->totalNumInsts = 0;
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}
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TimingSimpleCPU::~TimingSimpleCPU()
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{
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}
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void
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TimingSimpleCPU::serialize(ostream &os)
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{
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SimObject::State so_state = SimObject::getState();
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SERIALIZE_ENUM(so_state);
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BaseSimpleCPU::serialize(os);
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}
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void
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TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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SimObject::State so_state;
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UNSERIALIZE_ENUM(so_state);
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BaseSimpleCPU::unserialize(cp, section);
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}
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unsigned int
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TimingSimpleCPU::drain(Event *drain_event)
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{
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// TimingSimpleCPU is ready to drain if it's not waiting for
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// an access to complete.
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if (_status == Idle || _status == Running || _status == SwitchedOut) {
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changeState(SimObject::Drained);
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return 0;
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} else {
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changeState(SimObject::Draining);
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drainEvent = drain_event;
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return 1;
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}
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}
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void
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TimingSimpleCPU::resume()
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{
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DPRINTF(SimpleCPU, "Resume\n");
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if (_status != SwitchedOut && _status != Idle) {
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assert(system->getMemoryMode() == Enums::timing);
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if (fetchEvent.scheduled())
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deschedule(fetchEvent);
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schedule(fetchEvent, nextCycle());
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}
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changeState(SimObject::Running);
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}
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void
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TimingSimpleCPU::switchOut()
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{
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assert(_status == Running || _status == Idle);
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_status = SwitchedOut;
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numCycles += tickToCycles(curTick() - previousTick);
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// If we've been scheduled to resume but are then told to switch out,
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// we'll need to cancel it.
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if (fetchEvent.scheduled())
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deschedule(fetchEvent);
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}
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void
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TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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_status = Running;
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break;
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}
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}
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if (_status != Running) {
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_status = Idle;
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}
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assert(threadContexts.size() == 1);
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previousTick = curTick();
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}
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void
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TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
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{
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DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
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assert(thread_num == 0);
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assert(thread);
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assert(_status == Idle);
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notIdleFraction++;
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_status = Running;
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// kick things off by initiating the fetch of the next instruction
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schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
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}
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void
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TimingSimpleCPU::suspendContext(ThreadID thread_num)
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{
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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assert(thread_num == 0);
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assert(thread);
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if (_status == Idle)
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return;
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assert(_status == Running);
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// just change status to Idle... if status != Running,
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// completeInst() will not initiate fetch of next instruction.
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notIdleFraction--;
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_status = Idle;
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}
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bool
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TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
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{
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RequestPtr req = pkt->req;
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if (req->isMmappedIpr()) {
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Tick delay;
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delay = TheISA::handleIprRead(thread->getTC(), pkt);
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new IprEvent(pkt, this, nextCycle(curTick() + delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTiming(pkt)) {
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_status = DcacheRetry;
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dcache_pkt = pkt;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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return dcache_pkt == NULL;
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}
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void
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TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
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bool read)
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{
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PacketPtr pkt;
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buildPacket(pkt, req, read);
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pkt->dataDynamicArray<uint8_t>(data);
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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assert(!dcache_pkt);
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pkt->makeResponse();
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completeDataAccess(pkt);
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} else if (read) {
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handleReadPacket(pkt);
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} else {
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bool do_access = true; // flag to suppress cache access
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if (req->isLLSC()) {
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do_access = TheISA::handleLockedWrite(thread, req);
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} else if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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if (do_access) {
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dcache_pkt = pkt;
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handleWritePacket();
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} else {
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_status = DcacheWaitResponse;
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completeDataAccess(pkt);
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}
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}
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}
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void
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TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
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RequestPtr req, uint8_t *data, bool read)
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{
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PacketPtr pkt1, pkt2;
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buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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assert(!dcache_pkt);
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pkt1->makeResponse();
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completeDataAccess(pkt1);
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} else if (read) {
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SplitFragmentSenderState * send_state =
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dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
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if (handleReadPacket(pkt1)) {
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send_state->clearFromParent();
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send_state = dynamic_cast<SplitFragmentSenderState *>(
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pkt2->senderState);
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if (handleReadPacket(pkt2)) {
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send_state->clearFromParent();
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}
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}
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} else {
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dcache_pkt = pkt1;
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SplitFragmentSenderState * send_state =
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dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
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if (handleWritePacket()) {
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send_state->clearFromParent();
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dcache_pkt = pkt2;
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send_state = dynamic_cast<SplitFragmentSenderState *>(
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pkt2->senderState);
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if (handleWritePacket()) {
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send_state->clearFromParent();
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}
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}
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}
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}
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void
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TimingSimpleCPU::translationFault(Fault fault)
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{
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// fault may be NoFault in cases where a fault is suppressed,
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// for instance prefetches.
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numCycles += tickToCycles(curTick() - previousTick);
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previousTick = curTick();
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if (traceData) {
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// Since there was a fault, we shouldn't trace this instruction.
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delete traceData;
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traceData = NULL;
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}
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postExecute();
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if (getState() == SimObject::Draining) {
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advancePC(fault);
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completeDrain();
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} else {
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advanceInst(fault);
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}
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}
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void
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TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
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{
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MemCmd cmd;
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if (read) {
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cmd = MemCmd::ReadReq;
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if (req->isLLSC())
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cmd = MemCmd::LoadLockedReq;
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} else {
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cmd = MemCmd::WriteReq;
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if (req->isLLSC()) {
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cmd = MemCmd::StoreCondReq;
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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}
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}
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pkt = new Packet(req, cmd, Packet::Broadcast);
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}
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void
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TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read)
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{
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pkt1 = pkt2 = NULL;
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assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
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if (req->getFlags().isSet(Request::NO_ACCESS)) {
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buildPacket(pkt1, req, read);
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return;
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}
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buildPacket(pkt1, req1, read);
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buildPacket(pkt2, req2, read);
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req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
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PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
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Packet::Broadcast);
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pkt->dataDynamicArray<uint8_t>(data);
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pkt1->dataStatic<uint8_t>(data);
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pkt2->dataStatic<uint8_t>(data + req1->getSize());
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SplitMainSenderState * main_send_state = new SplitMainSenderState;
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pkt->senderState = main_send_state;
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main_send_state->fragments[0] = pkt1;
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main_send_state->fragments[1] = pkt2;
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main_send_state->outstanding = 2;
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pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
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pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
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}
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Fault
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TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
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unsigned size, unsigned flags)
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{
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Fault fault;
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const int asid = 0;
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const ThreadID tid = 0;
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const Addr pc = thread->instAddr();
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unsigned block_size = dcachePort.peerBlockSize();
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BaseTLB::Mode mode = BaseTLB::Read;
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if (traceData) {
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traceData->setAddr(addr);
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}
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RequestPtr req = new Request(asid, addr, size,
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flags, dataMasterId(), pc, _cpuId, tid);
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Addr split_addr = roundDown(addr + size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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_status = DTBWaitResponse;
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if (split_addr > addr) {
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RequestPtr req1, req2;
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assert(!req->isLLSC() && !req->isSwap());
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req->splitOnVaddr(split_addr, req1, req2);
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WholeTranslationState *state =
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new WholeTranslationState(req, req1, req2, new uint8_t[size],
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NULL, mode);
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DataTranslation<TimingSimpleCPU *> *trans1 =
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new DataTranslation<TimingSimpleCPU *>(this, state, 0);
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DataTranslation<TimingSimpleCPU *> *trans2 =
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new DataTranslation<TimingSimpleCPU *>(this, state, 1);
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thread->dtb->translateTiming(req1, tc, trans1, mode);
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thread->dtb->translateTiming(req2, tc, trans2, mode);
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} else {
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WholeTranslationState *state =
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new WholeTranslationState(req, new uint8_t[size], NULL, mode);
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DataTranslation<TimingSimpleCPU *> *translation
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= new DataTranslation<TimingSimpleCPU *>(this, state);
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thread->dtb->translateTiming(req, tc, translation, mode);
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}
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return NoFault;
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}
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bool
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TimingSimpleCPU::handleWritePacket()
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{
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RequestPtr req = dcache_pkt->req;
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if (req->isMmappedIpr()) {
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Tick delay;
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delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
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new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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} else if (!dcachePort.sendTiming(dcache_pkt)) {
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_status = DcacheRetry;
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} else {
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_status = DcacheWaitResponse;
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// memory system takes ownership of packet
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dcache_pkt = NULL;
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}
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return dcache_pkt == NULL;
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}
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|
|
Fault
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TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
|
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Addr addr, unsigned flags, uint64_t *res)
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{
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uint8_t *newData = new uint8_t[size];
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memcpy(newData, data, size);
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|
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const int asid = 0;
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const ThreadID tid = 0;
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const Addr pc = thread->instAddr();
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unsigned block_size = dcachePort.peerBlockSize();
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BaseTLB::Mode mode = BaseTLB::Write;
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if (traceData) {
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traceData->setAddr(addr);
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}
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RequestPtr req = new Request(asid, addr, size,
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flags, dataMasterId(), pc, _cpuId, tid);
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Addr split_addr = roundDown(addr + size - 1, block_size);
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assert(split_addr <= addr || split_addr - addr < block_size);
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_status = DTBWaitResponse;
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if (split_addr > addr) {
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RequestPtr req1, req2;
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assert(!req->isLLSC() && !req->isSwap());
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req->splitOnVaddr(split_addr, req1, req2);
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WholeTranslationState *state =
|
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new WholeTranslationState(req, req1, req2, newData, res, mode);
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DataTranslation<TimingSimpleCPU *> *trans1 =
|
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new DataTranslation<TimingSimpleCPU *>(this, state, 0);
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|
DataTranslation<TimingSimpleCPU *> *trans2 =
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
|
|
|
|
thread->dtb->translateTiming(req1, tc, trans1, mode);
|
|
thread->dtb->translateTiming(req2, tc, trans2, mode);
|
|
} else {
|
|
WholeTranslationState *state =
|
|
new WholeTranslationState(req, newData, res, mode);
|
|
DataTranslation<TimingSimpleCPU *> *translation =
|
|
new DataTranslation<TimingSimpleCPU *>(this, state);
|
|
thread->dtb->translateTiming(req, tc, translation, mode);
|
|
}
|
|
|
|
// Translation faults will be returned via finishTranslation()
|
|
return NoFault;
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
|
|
{
|
|
_status = Running;
|
|
|
|
if (state->getFault() != NoFault) {
|
|
if (state->isPrefetch()) {
|
|
state->setNoFault();
|
|
}
|
|
delete [] state->data;
|
|
state->deleteReqs();
|
|
translationFault(state->getFault());
|
|
} else {
|
|
if (!state->isSplit) {
|
|
sendData(state->mainReq, state->data, state->res,
|
|
state->mode == BaseTLB::Read);
|
|
} else {
|
|
sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
|
|
state->data, state->mode == BaseTLB::Read);
|
|
}
|
|
}
|
|
|
|
delete state;
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::fetch()
|
|
{
|
|
DPRINTF(SimpleCPU, "Fetch\n");
|
|
|
|
if (!curStaticInst || !curStaticInst->isDelayedCommit())
|
|
checkForInterrupts();
|
|
|
|
checkPcEventQueue();
|
|
|
|
// We must have just got suspended by a PC event
|
|
if (_status == Idle)
|
|
return;
|
|
|
|
TheISA::PCState pcState = thread->pcState();
|
|
bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
|
|
|
|
if (needToFetch) {
|
|
_status = Running;
|
|
Request *ifetch_req = new Request();
|
|
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
|
|
setupFetchRequest(ifetch_req);
|
|
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
|
|
thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
|
|
BaseTLB::Execute);
|
|
} else {
|
|
_status = IcacheWaitResponse;
|
|
completeIfetch(NULL);
|
|
|
|
numCycles += tickToCycles(curTick() - previousTick);
|
|
previousTick = curTick();
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
|
|
{
|
|
if (fault == NoFault) {
|
|
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
|
|
req->getVaddr(), req->getPaddr());
|
|
ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
|
|
ifetch_pkt->dataStatic(&inst);
|
|
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
|
|
|
|
if (!icachePort.sendTiming(ifetch_pkt)) {
|
|
// Need to wait for retry
|
|
_status = IcacheRetry;
|
|
} else {
|
|
// Need to wait for cache to respond
|
|
_status = IcacheWaitResponse;
|
|
// ownership of packet transferred to memory system
|
|
ifetch_pkt = NULL;
|
|
}
|
|
} else {
|
|
DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
|
|
delete req;
|
|
// fetch fault: advance directly to next instruction (fault handler)
|
|
_status = Running;
|
|
advanceInst(fault);
|
|
}
|
|
|
|
numCycles += tickToCycles(curTick() - previousTick);
|
|
previousTick = curTick();
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::advanceInst(Fault fault)
|
|
{
|
|
|
|
if (_status == Faulting)
|
|
return;
|
|
|
|
if (fault != NoFault) {
|
|
advancePC(fault);
|
|
DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
|
|
reschedule(fetchEvent, nextCycle(), true);
|
|
_status = Faulting;
|
|
return;
|
|
}
|
|
|
|
|
|
if (!stayAtPC)
|
|
advancePC(fault);
|
|
|
|
if (_status == Running) {
|
|
// kick off fetch of next instruction... callback from icache
|
|
// response will cause that instruction to be executed,
|
|
// keeping the CPU running.
|
|
fetch();
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
|
|
{
|
|
DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
|
|
pkt->getAddr() : 0);
|
|
|
|
// received a response from the icache: execute the received
|
|
// instruction
|
|
|
|
assert(!pkt || !pkt->isError());
|
|
assert(_status == IcacheWaitResponse);
|
|
|
|
_status = Running;
|
|
|
|
numCycles += tickToCycles(curTick() - previousTick);
|
|
previousTick = curTick();
|
|
|
|
if (getState() == SimObject::Draining) {
|
|
if (pkt) {
|
|
delete pkt->req;
|
|
delete pkt;
|
|
}
|
|
|
|
completeDrain();
|
|
return;
|
|
}
|
|
|
|
preExecute();
|
|
if (curStaticInst && curStaticInst->isMemRef()) {
|
|
// load or store: just send to dcache
|
|
Fault fault = curStaticInst->initiateAcc(this, traceData);
|
|
|
|
// If we're not running now the instruction will complete in a dcache
|
|
// response callback or the instruction faulted and has started an
|
|
// ifetch
|
|
if (_status == Running) {
|
|
if (fault != NoFault && traceData) {
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
postExecute();
|
|
// @todo remove me after debugging with legion done
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
curStaticInst->isFirstMicroop()))
|
|
instCnt++;
|
|
advanceInst(fault);
|
|
}
|
|
} else if (curStaticInst) {
|
|
// non-memory instruction: execute completely now
|
|
Fault fault = curStaticInst->execute(this, traceData);
|
|
|
|
// keep an instruction count
|
|
if (fault == NoFault)
|
|
countInst();
|
|
else if (traceData && !DTRACE(ExecFaulting)) {
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
postExecute();
|
|
// @todo remove me after debugging with legion done
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
curStaticInst->isFirstMicroop()))
|
|
instCnt++;
|
|
advanceInst(fault);
|
|
} else {
|
|
advanceInst(NoFault);
|
|
}
|
|
|
|
if (pkt) {
|
|
delete pkt->req;
|
|
delete pkt;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IcachePort::ITickEvent::process()
|
|
{
|
|
cpu->completeIfetch(pkt);
|
|
}
|
|
|
|
bool
|
|
TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isResponse());
|
|
if (!pkt->wasNacked()) {
|
|
DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
|
|
// delay processing of returned data until next CPU clock edge
|
|
Tick next_tick = cpu->nextCycle(curTick());
|
|
|
|
if (next_tick == curTick())
|
|
cpu->completeIfetch(pkt);
|
|
else
|
|
tickEvent.schedule(pkt, next_tick);
|
|
|
|
return true;
|
|
} else {
|
|
assert(cpu->_status == IcacheWaitResponse);
|
|
pkt->reinitNacked();
|
|
if (!sendTiming(pkt)) {
|
|
cpu->_status = IcacheRetry;
|
|
cpu->ifetch_pkt = pkt;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IcachePort::recvRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->ifetch_pkt != NULL);
|
|
assert(cpu->_status == IcacheRetry);
|
|
PacketPtr tmp = cpu->ifetch_pkt;
|
|
if (sendTiming(tmp)) {
|
|
cpu->_status = IcacheWaitResponse;
|
|
cpu->ifetch_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
|
|
{
|
|
// received a response from the dcache: complete the load or store
|
|
// instruction
|
|
assert(!pkt->isError());
|
|
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
|
|
pkt->req->getFlags().isSet(Request::NO_ACCESS));
|
|
|
|
numCycles += tickToCycles(curTick() - previousTick);
|
|
previousTick = curTick();
|
|
|
|
if (pkt->senderState) {
|
|
SplitFragmentSenderState * send_state =
|
|
dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
|
|
assert(send_state);
|
|
delete pkt->req;
|
|
delete pkt;
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
|
delete send_state;
|
|
|
|
SplitMainSenderState * main_send_state =
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
assert(main_send_state);
|
|
// Record the fact that this packet is no longer outstanding.
|
|
assert(main_send_state->outstanding != 0);
|
|
main_send_state->outstanding--;
|
|
|
|
if (main_send_state->outstanding) {
|
|
return;
|
|
} else {
|
|
delete main_send_state;
|
|
big_pkt->senderState = NULL;
|
|
pkt = big_pkt;
|
|
}
|
|
}
|
|
|
|
_status = Running;
|
|
|
|
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
|
|
|
|
// keep an instruction count
|
|
if (fault == NoFault)
|
|
countInst();
|
|
else if (traceData) {
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
delete traceData;
|
|
traceData = NULL;
|
|
}
|
|
|
|
// the locked flag may be cleared on the response packet, so check
|
|
// pkt->req and not pkt to see if it was a load-locked
|
|
if (pkt->isRead() && pkt->req->isLLSC()) {
|
|
TheISA::handleLockedRead(thread, pkt->req);
|
|
}
|
|
|
|
delete pkt->req;
|
|
delete pkt;
|
|
|
|
postExecute();
|
|
|
|
if (getState() == SimObject::Draining) {
|
|
advancePC(fault);
|
|
completeDrain();
|
|
|
|
return;
|
|
}
|
|
|
|
advanceInst(fault);
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::completeDrain()
|
|
{
|
|
DPRINTF(Config, "Done draining\n");
|
|
changeState(SimObject::Drained);
|
|
drainEvent->process();
|
|
}
|
|
|
|
bool
|
|
TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
|
|
{
|
|
assert(pkt->isResponse());
|
|
if (!pkt->wasNacked()) {
|
|
// delay processing of returned data until next CPU clock edge
|
|
Tick next_tick = cpu->nextCycle(curTick());
|
|
|
|
if (next_tick == curTick()) {
|
|
cpu->completeDataAccess(pkt);
|
|
} else {
|
|
if (!tickEvent.scheduled()) {
|
|
tickEvent.schedule(pkt, next_tick);
|
|
} else {
|
|
// In the case of a split transaction and a cache that is
|
|
// faster than a CPU we could get two responses before
|
|
// next_tick expires
|
|
if (!retryEvent.scheduled())
|
|
cpu->schedule(retryEvent, next_tick);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
} else {
|
|
assert(cpu->_status == DcacheWaitResponse);
|
|
pkt->reinitNacked();
|
|
if (!sendTiming(pkt)) {
|
|
cpu->_status = DcacheRetry;
|
|
cpu->dcache_pkt = pkt;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::DTickEvent::process()
|
|
{
|
|
cpu->completeDataAccess(pkt);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::DcachePort::recvRetry()
|
|
{
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
// waiting to transmit
|
|
assert(cpu->dcache_pkt != NULL);
|
|
assert(cpu->_status == DcacheRetry);
|
|
PacketPtr tmp = cpu->dcache_pkt;
|
|
if (tmp->senderState) {
|
|
// This is a packet from a split access.
|
|
SplitFragmentSenderState * send_state =
|
|
dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
|
|
assert(send_state);
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
|
|
|
SplitMainSenderState * main_send_state =
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
assert(main_send_state);
|
|
|
|
if (sendTiming(tmp)) {
|
|
// If we were able to send without retrying, record that fact
|
|
// and try sending the other fragment.
|
|
send_state->clearFromParent();
|
|
int other_index = main_send_state->getPendingFragment();
|
|
if (other_index > 0) {
|
|
tmp = main_send_state->fragments[other_index];
|
|
cpu->dcache_pkt = tmp;
|
|
if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
|
|
(big_pkt->isWrite() && cpu->handleWritePacket())) {
|
|
main_send_state->fragments[other_index] = NULL;
|
|
}
|
|
} else {
|
|
cpu->_status = DcacheWaitResponse;
|
|
// memory system takes ownership of packet
|
|
cpu->dcache_pkt = NULL;
|
|
}
|
|
}
|
|
} else if (sendTiming(tmp)) {
|
|
cpu->_status = DcacheWaitResponse;
|
|
// memory system takes ownership of packet
|
|
cpu->dcache_pkt = NULL;
|
|
}
|
|
}
|
|
|
|
TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
|
|
Tick t)
|
|
: pkt(_pkt), cpu(_cpu)
|
|
{
|
|
cpu->schedule(this, t);
|
|
}
|
|
|
|
void
|
|
TimingSimpleCPU::IprEvent::process()
|
|
{
|
|
cpu->completeDataAccess(pkt);
|
|
}
|
|
|
|
const char *
|
|
TimingSimpleCPU::IprEvent::description() const
|
|
{
|
|
return "Timing Simple CPU Delay IPR event";
|
|
}
|
|
|
|
|
|
void
|
|
TimingSimpleCPU::printAddr(Addr a)
|
|
{
|
|
dcachePort.printAddr(a);
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// TimingSimpleCPU Simulation Object
|
|
//
|
|
TimingSimpleCPU *
|
|
TimingSimpleCPUParams::create()
|
|
{
|
|
numThreads = 1;
|
|
if (!FullSystem && workload.size() != 1)
|
|
panic("only one workload allowed");
|
|
return new TimingSimpleCPU(this);
|
|
}
|