481eb6ae80
Another churn to clean up undefined behaviour, mostly ARM, but some parts also touching the generic part of the code base. Most of the fixes are simply ensuring that proper intialisation. One of the more subtle changes is the return type of the sign-extension, which is changed to uint64_t. This is to avoid shifting negative values (undefined behaviour) in the ISA code.
362 lines
11 KiB
C++
362 lines
11 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
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#define __ARCH_ARM_INSTS_PREDINST_HH__
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#include "arch/arm/insts/static_inst.hh"
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#include "base/trace.hh"
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namespace ArmISA
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{
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static inline uint32_t
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rotate_imm(uint32_t immValue, uint32_t rotateValue)
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{
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rotateValue &= 31;
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return rotateValue == 0 ? immValue :
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(immValue >> rotateValue) | (immValue << (32 - rotateValue));
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}
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static inline uint32_t
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modified_imm(uint8_t ctrlImm, uint8_t dataImm)
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{
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uint32_t bigData = dataImm;
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uint32_t bigCtrl = ctrlImm;
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if (bigCtrl < 4) {
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switch (bigCtrl) {
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case 0:
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return bigData;
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case 1:
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return bigData | (bigData << 16);
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case 2:
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return (bigData << 8) | (bigData << 24);
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case 3:
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return (bigData << 0) | (bigData << 8) |
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(bigData << 16) | (bigData << 24);
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}
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}
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bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
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bigData |= (1 << 7);
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return bigData << (32 - bigCtrl);
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}
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static inline uint64_t
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simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
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bool isAarch64 = false)
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{
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uint64_t bigData = data;
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immValid = true;
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switch (cmode) {
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case 0x0:
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case 0x1:
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bigData = (bigData << 0) | (bigData << 32);
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break;
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case 0x2:
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case 0x3:
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bigData = (bigData << 8) | (bigData << 40);
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break;
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case 0x4:
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case 0x5:
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bigData = (bigData << 16) | (bigData << 48);
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break;
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case 0x6:
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case 0x7:
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bigData = (bigData << 24) | (bigData << 56);
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break;
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case 0x8:
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case 0x9:
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bigData = (bigData << 0) | (bigData << 16) |
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(bigData << 32) | (bigData << 48);
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break;
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case 0xa:
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case 0xb:
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bigData = (bigData << 8) | (bigData << 24) |
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(bigData << 40) | (bigData << 56);
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break;
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case 0xc:
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bigData = (0xffULL << 0) | (bigData << 8) |
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(0xffULL << 32) | (bigData << 40);
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break;
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case 0xd:
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bigData = (0xffffULL << 0) | (bigData << 16) |
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(0xffffULL << 32) | (bigData << 48);
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break;
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case 0xe:
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if (op) {
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bigData = 0;
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for (int i = 7; i >= 0; i--) {
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if (bits(data, i)) {
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bigData |= (ULL(0xFF) << (i * 8));
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}
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}
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} else {
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bigData = (bigData << 0) | (bigData << 8) |
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(bigData << 16) | (bigData << 24) |
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(bigData << 32) | (bigData << 40) |
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(bigData << 48) | (bigData << 56);
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}
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break;
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case 0xf:
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{
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uint64_t bVal = 0;
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if (!op) {
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bVal = bits(bigData, 6) ? (0x1F) : (0x20);
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bigData = (bits(bigData, 5, 0) << 19) |
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(bVal << 25) | (bits(bigData, 7) << 31);
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bigData |= (bigData << 32);
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break;
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} else if (isAarch64) {
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bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
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bigData = (bits(bigData, 5, 0) << 48) |
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(bVal << 54) | (bits(bigData, 7) << 63);
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break;
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}
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}
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// Fall through, immediate encoding is invalid.
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default:
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immValid = false;
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break;
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}
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return bigData;
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}
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static inline uint64_t
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vfp_modified_imm(uint8_t data, bool wide)
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{
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uint64_t bigData = data;
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uint64_t repData;
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if (wide) {
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repData = bits(data, 6) ? 0xFF : 0;
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bigData = (bits(bigData, 5, 0) << 48) |
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(repData << 54) | (bits(~bigData, 6) << 62) |
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(bits(bigData, 7) << 63);
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} else {
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repData = bits(data, 6) ? 0x1F : 0;
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bigData = (bits(bigData, 5, 0) << 19) |
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(repData << 25) | (bits(~bigData, 6) << 30) |
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(bits(bigData, 7) << 31);
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}
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return bigData;
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}
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/**
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* Base class for predicated integer operations.
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*/
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class PredOp : public ArmStaticInst
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{
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protected:
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ConditionCode condCode;
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/// Constructor
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PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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ArmStaticInst(mnem, _machInst, __opClass)
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{
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if (machInst.aarch64)
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condCode = COND_UC;
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else if (machInst.itstateMask)
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condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
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else
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condCode = (ConditionCode)(unsigned)machInst.condCode;
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}
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};
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/**
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* Base class for predicated immediate operations.
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*/
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class PredImmOp : public PredOp
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{
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protected:
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uint32_t imm;
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uint32_t rotated_imm;
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uint32_t rotated_carry;
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uint32_t rotate;
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/// Constructor
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PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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PredOp(mnem, _machInst, __opClass),
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imm(machInst.imm), rotated_imm(0), rotated_carry(0),
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rotate(machInst.rotate << 1)
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{
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rotated_imm = rotate_imm(imm, rotate);
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if (rotate != 0)
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rotated_carry = bits(rotated_imm, 31);
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for predicated integer operations.
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*/
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class PredIntOp : public PredOp
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{
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protected:
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uint32_t shift_size;
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uint32_t shift;
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/// Constructor
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PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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PredOp(mnem, _machInst, __opClass),
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shift_size(machInst.shiftSize), shift(machInst.shift)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataImmOp : public PredOp
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{
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protected:
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IntRegIndex dest, op1;
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uint32_t imm;
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// Whether the carry flag should be modified if that's an option for
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// this instruction.
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bool rotC;
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DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataRegOp : public PredOp
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{
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protected:
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IntRegIndex dest, op1, op2;
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int32_t shiftAmt;
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ArmShiftType shiftType;
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DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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int32_t _shiftAmt, ArmShiftType _shiftType) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2),
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shiftAmt(_shiftAmt), shiftType(_shiftType)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class DataRegRegOp : public PredOp
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{
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protected:
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IntRegIndex dest, op1, op2, shift;
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ArmShiftType shiftType;
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DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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IntRegIndex _shift, ArmShiftType _shiftType) :
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PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), op2(_op2), shift(_shift),
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shiftType(_shiftType)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for predicated macro-operations.
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*/
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class PredMacroOp : public PredOp
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{
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protected:
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uint32_t numMicroops;
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StaticInstPtr * microOps;
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/// Constructor
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PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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PredOp(mnem, _machInst, __opClass),
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numMicroops(0), microOps(nullptr)
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{
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// We rely on the subclasses of this object to handle the
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// initialization of the micro-operations, since they are
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// all of variable length
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flags[IsMacroop] = true;
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}
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~PredMacroOp()
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{
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if (numMicroops)
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delete [] microOps;
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}
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StaticInstPtr
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fetchMicroop(MicroPC microPC) const
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{
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assert(microPC < numMicroops);
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return microOps[microPC];
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for predicated micro-operations.
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*/
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class PredMicroop : public PredOp
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{
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/// Constructor
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PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
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PredOp(mnem, _machInst, __opClass)
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{
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flags[IsMicroop] = true;
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}
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void
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advancePC(PCState &pcState) const
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{
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if (flags[IsLastMicroop])
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pcState.uEnd();
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else
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pcState.uAdvance();
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}
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};
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}
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#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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