134 lines
5.1 KiB
Python
134 lines
5.1 KiB
Python
#
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# Copyright (c) 2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its contributors
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# may be used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Sooraj Puthoor, Lisa Hsu
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#
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import convert
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from CntrlBase import *
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from Cluster import Cluster
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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latency = 1
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resourceStalls = False
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def create(self, size, assoc, options):
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self.size = MemorySize(size)
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self.assoc = assoc
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self.replacement_policy = PseudoLRUReplacementPolicy()
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 10
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resourceStalls = False
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def create(self, size, assoc, options):
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self.size = MemorySize(size)
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self.assoc = assoc
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self.replacement_policy = PseudoLRUReplacementPolicy()
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class CPCntrl(AMD_Base_Controller, CntrlBase):
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def create(self, options, ruby_system, system):
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self.version = self.versionCount()
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self.cntrl_id = self.cntrlCount()
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self.L1Icache = L1Cache()
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self.L1Icache.create(options.l1i_size, options.l1i_assoc, options)
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self.L1D0cache = L1Cache()
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self.L1D0cache.create(options.l1d_size, options.l1d_assoc, options)
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self.L1D1cache = L1Cache()
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self.L1D1cache.create(options.l1d_size, options.l1d_assoc, options)
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self.L2cache = L2Cache()
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self.L2cache.create(options.l2_size, options.l2_assoc, options)
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self.sequencer = RubySequencer()
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self.sequencer.version = self.seqCount()
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self.sequencer.icache = self.L1Icache
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self.sequencer.dcache = self.L1D0cache
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self.sequencer.ruby_system = ruby_system
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self.sequencer.coreid = 0
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self.sequencer.is_cpu_sequencer = True
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self.sequencer1 = RubySequencer()
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self.sequencer1.version = self.seqCount()
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self.sequencer1.icache = self.L1Icache
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self.sequencer1.dcache = self.L1D1cache
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self.sequencer1.ruby_system = ruby_system
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self.sequencer1.coreid = 1
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self.sequencer1.is_cpu_sequencer = True
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self.issue_latency = options.cpu_to_dir_latency
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self.send_evictions = send_evicts(options)
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self.ruby_system = ruby_system
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if options.recycle_latency:
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self.recycle_latency = options.recycle_latency
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def define_options(parser):
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parser.add_option("--cpu-to-dir-latency", type="int", default=15)
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def construct(options, system, ruby_system):
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if (buildEnv['PROTOCOL'] != 'GPU_VIPER' or
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buildEnv['PROTOCOL'] != 'GPU_VIPER_Region' or
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buildEnv['PROTOCOL'] != 'GPU_VIPER_Baseline'):
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panic("This script requires VIPER based protocols \
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to be built.")
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cpu_sequencers = []
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cpuCluster = None
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cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s
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for i in xrange((options.num_cpus + 1) / 2):
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cp_cntrl = CPCntrl()
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cp_cntrl.create(options, ruby_system, system)
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# Connect the CP controllers to the ruby network
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cp_cntrl.requestFromCore = ruby_system.network.slave
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cp_cntrl.responseFromCore = ruby_system.network.slave
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cp_cntrl.unblockFromCore = ruby_system.network.slave
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cp_cntrl.probeToCore = ruby_system.network.master
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cp_cntrl.responseToCore = ruby_system.network.master
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exec("system.cp_cntrl%d = cp_cntrl" % i)
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.extend([cp_cntrl.sequencer, cp_cntrl.sequencer1])
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cpuCluster.add(cp_cntrl)
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return cpu_sequencers, cpuCluster
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