gem5/src/sim
Nathan Binkert afed455e77 Expose debugBreakCycle through swig and get rid of
the Debug param context

--HG--
extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
2006-11-13 12:20:08 -08:00
..
async.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
builder.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
builder.hh fixes for gcc 4.1 2006-08-15 17:41:22 -04:00
byteswap.hh fixes so that M5 will compile under solaris 2006-11-04 21:41:01 -05:00
debug.cc Expose debugBreakCycle through swig and get rid of 2006-11-13 12:20:08 -08:00
debug.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
eventq.cc Move main control from C++ into Python. 2006-06-09 23:01:31 -04:00
eventq.hh Add new event priority for trace enable events so 2006-10-19 10:21:23 -07:00
faults.cc Tweak a few things for better page fault debugging. 2006-10-21 05:28:05 -04:00
faults.hh add syscall emulation page table fault so we can allocate more stack pages 2006-06-26 16:49:05 -04:00
host.hh simplify maxtick parsing in both the python and the c++. 2006-11-08 15:05:23 -05:00
main.cc Expose debugBreakCycle through swig and get rid of 2006-11-13 12:20:08 -08:00
param.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
param.hh fix endian issues with condition codes 2006-11-10 20:17:42 -05:00
process.cc add code to serialize se structures. Lisa is working on the python side of things and will test 2006-10-17 19:38:36 -04:00
process.hh add code to serialize se structures. Lisa is working on the python side of things and will test 2006-10-17 19:38:36 -04:00
pseudo_inst.cc Get rid of the ParamContext for pseudo instructions and move 2006-11-11 17:22:10 -08:00
pseudo_inst.hh Cleaned up remnants of ivlb and ivle 2006-11-06 20:49:48 -05:00
root.cc there are two main thrusts of this changeset. 2006-10-06 01:27:02 -04:00
serialize.cc Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
serialize.hh Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint(). 2006-07-07 16:46:08 -04:00
sim_events.cc there are two main thrusts of this changeset. 2006-10-06 01:27:02 -04:00
sim_events.hh there are two main thrusts of this changeset. 2006-10-06 01:27:02 -04:00
sim_exit.hh there are two main thrusts of this changeset. 2006-10-06 01:27:02 -04:00
sim_object.cc remove connectAll() and connect() code since it isn't used anymore. (The python does it all) 2006-10-31 13:23:49 -05:00
sim_object.hh remove connectAll() and connect() code since it isn't used anymore. (The python does it all) 2006-10-31 13:23:49 -05:00
startup.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
startup.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
stat_control.cc fix the argument to m5.simulate() on a checkpoint. 2006-10-05 13:18:32 -04:00
stat_control.hh Merge ktlim@zamp:./local/clean/o3-merge/m5 2006-09-30 23:43:23 -04:00
stats.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
syscall_emul.cc Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters. 2006-09-17 03:00:55 -04:00
syscall_emul.hh Added in missing portions of the stat structure copying function. 2006-10-15 21:54:59 -04:00
system.cc Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not. 2006-11-06 18:29:58 -05:00
system.hh Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not. 2006-11-06 18:29:58 -05:00
vptr.hh Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00