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gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
Kevin Lim d70f01ba5c Update refs for new CPU frequency changes. 
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout:
tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini:
tests/quick/50.memtest/ref/alpha/linux/memtest/config.out:
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt:
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout:
    Update refs

--HG--
extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
2007-04-22 14:50:37 -04:00

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[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=TimingSimpleCPU
children=dcache icache l2cache toL2Bus workload
clock=500
cpu_id=0
defer_registration=false
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
system=system
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=262144
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=131072
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
adaptive_compression=false
assoc=2
block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
hit_latency=1
latency=1
lifo=false
max_miss_count=0
mshrs=10
prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
prefetch_serial_squash=false
prefetch_use_cpu_id=true
prefetcher_size=100
prioritizeRequests=false
protocol=Null
repl=Null
size=2097152
split=false
split_size=0
store_compressed=false
subblock_size=0
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.port[2]
mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
euid=100
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]
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