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gem5/tests/test1/ref/alpha/detailed/config.ini
Kevin Lim 4bd025742d Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model> 
Right now only non-SMT SE regression tests have been added back in.  The rest are pending getting SMT working, and consolidating the FS configuration files.

Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.

Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work.  The test itself should probably work once the code is fixed.

SConstruct:
    Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
    Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.

--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
2006-07-19 16:07:25 -04:00

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[root]
type=Root
children=system
checkpoint=
clock=1000000000000
max_tick=0
output_file=cout
progress_interval=0
[debug]
break_cycles=
[exetrace]
intel_format=false
pc_symbol=true
print_cpseq=false
print_cycle=true
print_data=true
print_effaddr=true
print_fetchseq=false
print_iregs=false
print_opclass=true
print_thread=true
speculative=true
trace_system=client
[serialize]
count=10
cycle=0
dir=cpt.%012d
period=0
[stats]
descriptions=true
dump_cycle=0
dump_period=0
dump_reset=false
ignore_events=
mysql_db=
mysql_host=
mysql_password=
mysql_user=
project_name=test
simulation_name=test
simulation_sample=0
text_compat=true
text_file=m5stats.txt
[system]
type=System
children=cpu0 physmem workload
mem_mode=atomic
physmem=system.physmem
[system.cpu0]
type=DerivO3CPU
children=checker fuPool mem
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
LQEntries=32
RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
checker=system.cpu0.checker
choiceCtrBits=2
choicePredictorSize=8192
clock=1
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
defer_registration=false
dispatchWidth=8
fetchToDecodeDelay=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
issueToExecuteDelay=1
issueWidth=8
localCtrBits=2
localHistoryBits=11
localHistoryTableSize=2048
localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=500000
max_loads_all_threads=0
max_loads_any_thread=0
mem=system.cpu0.mem
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numThreads=1
predType=tournament
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
squashWidth=8
system=system
wbDepth=1
wbWidth=8
workload=system.workload
[system.cpu0.checker]
type=O3Checker
clock=1
defer_registration=false
exitOnError=true
function_trace=false
function_trace_start=0
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
system=system
warnOnlyOnLoadError=false
workload=system.workload
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList0
count=6
opList=system.cpu0.fuPool.FUList0.opList0
[system.cpu0.fuPool.FUList0.opList0]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList0
count=0
opList=system.cpu0.fuPool.FUList4.opList0
[system.cpu0.fuPool.FUList4.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList5]
type=FUDesc
children=opList0
count=0
opList=system.cpu0.fuPool.FUList5.opList0
[system.cpu0.fuPool.FUList5.opList0]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList6]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
[system.cpu0.fuPool.FUList6.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList6.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList0
count=1
opList=system.cpu0.fuPool.FUList7.opList0
[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu0.mem]
type=Bus
bus_id=0
[system.physmem]
type=PhysicalMemory
file=
latency=1
[system.workload]
type=EioProcess
chkpt=
file=/z/ktlim2/clean/newmem-merge/tests/test-progs/anagram/bin/anagram-vshort.eio.gz
output=cout
system=system
[trace]
bufsize=0
dump_on_exit=false
file=cout
flags=
ignore=
start=0
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