ed38e3432c
The drain() call currently passes around a DrainManager pointer, which is now completely pointless since there is only ever one global DrainManager in the system. It also contains vestiges from the time when SimObjects had to keep track of their child objects that needed draining. This changeset moves all of the DrainState handling to the Drainable base class and changes the drain() and drainResume() calls to reflect this. Particularly, the drain() call has been updated to take no parameters (the DrainManager argument isn't needed) and return a DrainState instead of an unsigned integer (there is no point returning anything other than 0 or 1 any more). Drainable objects should return either DrainState::Draining (equivalent to returning 1 in the old system) if they need more time to drain or DrainState::Drained (equivalent to returning 0 in the old system) if they are already in a consistent state. Returning DrainState::Running is considered an error. Drain done signalling is now done through the signalDrainDone() method in the Drainable class instead of using the DrainManager directly. The new call checks if the state of the object is DrainState::Draining before notifying the drain manager. This means that it is safe to call signalDrainDone() without first checking if the simulator has requested draining. The intention here is to reduce the code needed to implement draining in simple objects.
251 lines
8.2 KiB
C++
251 lines
8.2 KiB
C++
/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andrew Bardsley
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*/
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#include <algorithm>
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#include "cpu/minor/decode.hh"
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#include "cpu/minor/execute.hh"
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#include "cpu/minor/fetch1.hh"
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#include "cpu/minor/fetch2.hh"
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#include "cpu/minor/pipeline.hh"
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#include "debug/Drain.hh"
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#include "debug/MinorCPU.hh"
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#include "debug/MinorTrace.hh"
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#include "debug/Quiesce.hh"
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namespace Minor
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{
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Pipeline::Pipeline(MinorCPU &cpu_, MinorCPUParams ¶ms) :
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Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
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cpu(cpu_),
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allow_idling(params.enableIdling),
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f1ToF2(cpu.name() + ".f1ToF2", "lines",
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params.fetch1ToFetch2ForwardDelay),
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f2ToF1(cpu.name() + ".f2ToF1", "prediction",
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params.fetch1ToFetch2BackwardDelay, true),
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f2ToD(cpu.name() + ".f2ToD", "insts",
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params.fetch2ToDecodeForwardDelay),
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dToE(cpu.name() + ".dToE", "insts",
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params.decodeToExecuteForwardDelay),
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eToF1(cpu.name() + ".eToF1", "branch",
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params.executeBranchDelay),
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execute(cpu.name() + ".execute", cpu, params,
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dToE.output(), eToF1.input()),
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decode(cpu.name() + ".decode", cpu, params,
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f2ToD.output(), dToE.input(), execute.inputBuffer),
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fetch2(cpu.name() + ".fetch2", cpu, params,
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f1ToF2.output(), eToF1.output(), f2ToF1.input(), f2ToD.input(),
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decode.inputBuffer),
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fetch1(cpu.name() + ".fetch1", cpu, params,
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eToF1.output(), f1ToF2.input(), f2ToF1.output(), fetch2.inputBuffer),
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activityRecorder(cpu.name() + ".activity", Num_StageId,
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/* The max depth of inter-stage FIFOs */
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std::max(params.fetch1ToFetch2ForwardDelay,
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std::max(params.fetch2ToDecodeForwardDelay,
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std::max(params.decodeToExecuteForwardDelay,
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params.executeBranchDelay)))),
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needToSignalDrained(false)
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{
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if (params.fetch1ToFetch2ForwardDelay < 1) {
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fatal("%s: fetch1ToFetch2ForwardDelay must be >= 1 (%d)\n",
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cpu.name(), params.fetch1ToFetch2ForwardDelay);
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}
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if (params.fetch2ToDecodeForwardDelay < 1) {
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fatal("%s: fetch2ToDecodeForwardDelay must be >= 1 (%d)\n",
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cpu.name(), params.fetch2ToDecodeForwardDelay);
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}
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if (params.decodeToExecuteForwardDelay < 1) {
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fatal("%s: decodeToExecuteForwardDelay must be >= 1 (%d)\n",
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cpu.name(), params.decodeToExecuteForwardDelay);
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}
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if (params.executeBranchDelay < 1) {
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fatal("%s: executeBranchDelay must be >= 1\n",
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cpu.name(), params.executeBranchDelay);
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}
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}
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void
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Pipeline::minorTrace() const
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{
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fetch1.minorTrace();
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f1ToF2.minorTrace();
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f2ToF1.minorTrace();
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fetch2.minorTrace();
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f2ToD.minorTrace();
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decode.minorTrace();
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dToE.minorTrace();
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execute.minorTrace();
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eToF1.minorTrace();
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activityRecorder.minorTrace();
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}
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void
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Pipeline::evaluate()
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{
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/* Note that it's important to evaluate the stages in order to allow
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* 'immediate', 0-time-offset TimeBuffer activity to be visible from
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* later stages to earlier ones in the same cycle */
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execute.evaluate();
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decode.evaluate();
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fetch2.evaluate();
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fetch1.evaluate();
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if (DTRACE(MinorTrace))
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minorTrace();
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/* Update the time buffers after the stages */
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f1ToF2.evaluate();
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f2ToF1.evaluate();
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f2ToD.evaluate();
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dToE.evaluate();
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eToF1.evaluate();
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/* The activity recorder must be be called after all the stages and
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* before the idler (which acts on the advice of the activity recorder */
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activityRecorder.evaluate();
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if (allow_idling) {
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/* Become idle if we can but are not draining */
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if (!activityRecorder.active() && !needToSignalDrained) {
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DPRINTF(Quiesce, "Suspending as the processor is idle\n");
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stop();
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}
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/* Deactivate all stages. Note that the stages *could*
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* activate and deactivate themselves but that's fraught
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* with additional difficulty.
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* As organised herre */
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activityRecorder.deactivateStage(Pipeline::CPUStageId);
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activityRecorder.deactivateStage(Pipeline::Fetch1StageId);
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activityRecorder.deactivateStage(Pipeline::Fetch2StageId);
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activityRecorder.deactivateStage(Pipeline::DecodeStageId);
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activityRecorder.deactivateStage(Pipeline::ExecuteStageId);
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}
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if (needToSignalDrained) /* Must be draining */
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{
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DPRINTF(Drain, "Still draining\n");
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if (isDrained()) {
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DPRINTF(Drain, "Signalling end of draining\n");
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cpu.signalDrainDone();
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needToSignalDrained = false;
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stop();
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}
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}
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}
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MinorCPU::MinorCPUPort &
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Pipeline::getInstPort()
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{
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return fetch1.getIcachePort();
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}
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MinorCPU::MinorCPUPort &
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Pipeline::getDataPort()
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{
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return execute.getDcachePort();
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}
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void
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Pipeline::wakeupFetch()
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{
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execute.wakeupFetch();
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}
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bool
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Pipeline::drain()
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{
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DPRINTF(MinorCPU, "Draining pipeline by halting inst fetches. "
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" Execution should drain naturally\n");
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execute.drain();
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/* Make sure that needToSignalDrained isn't accidentally set if we
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* are 'pre-drained' */
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bool drained = isDrained();
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needToSignalDrained = !drained;
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return drained;
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}
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void
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Pipeline::drainResume()
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{
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DPRINTF(Drain, "Drain resume\n");
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execute.drainResume();
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}
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bool
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Pipeline::isDrained()
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{
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bool fetch1_drained = fetch1.isDrained();
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bool fetch2_drained = fetch2.isDrained();
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bool decode_drained = decode.isDrained();
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bool execute_drained = execute.isDrained();
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bool f1_to_f2_drained = f1ToF2.empty();
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bool f2_to_f1_drained = f2ToF1.empty();
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bool f2_to_d_drained = f2ToD.empty();
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bool d_to_e_drained = dToE.empty();
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bool ret = fetch1_drained && fetch2_drained &&
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decode_drained && execute_drained &&
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f1_to_f2_drained && f2_to_f1_drained &&
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f2_to_d_drained && d_to_e_drained;
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DPRINTF(MinorCPU, "Pipeline undrained stages state:%s%s%s%s%s%s%s%s\n",
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(fetch1_drained ? "" : " Fetch1"),
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(fetch2_drained ? "" : " Fetch2"),
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(decode_drained ? "" : " Decode"),
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(execute_drained ? "" : " Execute"),
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(f1_to_f2_drained ? "" : " F1->F2"),
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(f2_to_f1_drained ? "" : " F2->F1"),
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(f2_to_d_drained ? "" : " F2->D"),
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(d_to_e_drained ? "" : " D->E")
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);
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return ret;
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}
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}
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