123 lines
3.7 KiB
C++
123 lines
3.7 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*/
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#ifndef __CPU_INORDER_PARAMS_HH__
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#define __CPU_INORDER_PARAMS_HH__
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#include "cpu/base.hh"
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//Forward declarations
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class FunctionalMemory;
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class Process;
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class MemObject;
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class MemInterface;
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/**
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* This file defines the parameters that will be used for the InOrderCPU.
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* This must be defined externally so that the Impl can have a params class
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* defined that it can pass to all of the individual stages.
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*/
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class InOrderParams : public BaseCPU::Params
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{
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public:
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// Workloads
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std::vector<Process *> workload;
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Process *process;
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//
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// Memory System/Caches
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//
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unsigned cachePorts;
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std::string fetchMemPort;
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std::string dataMemPort;
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//
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// Branch predictor (BP & BTB)
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//
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std::string predType;
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unsigned localPredictorSize;
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unsigned localCtrBits;
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unsigned localHistoryTableSize;
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unsigned localHistoryBits;
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unsigned globalPredictorSize;
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unsigned globalCtrBits;
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unsigned globalHistoryBits;
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unsigned choicePredictorSize;
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unsigned choiceCtrBits;
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unsigned BTBEntries;
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unsigned BTBTagSize;
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unsigned RASSize;
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// Pipeline Parameters
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unsigned stageWidth;
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// InOrderCPU Simulation Parameters
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unsigned instShiftAmt;
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unsigned activity;
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unsigned deferRegistration;
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//
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// Memory Parameters
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//
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unsigned memBlockSize;
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//
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// Multiply Divide Unit
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//
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// @NOTE: If >1 MDU is needed and each MDU is to use varying parametesr,
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// then MDU must be defined as its own SimObject so that an arbitrary # can
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// be defined with different parameters
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/** Latency & Repeat Rate for Multiply Insts */
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unsigned multLatency;
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unsigned multRepeatRate;
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/** Latency & Repeat Rate for 8-bit Divide Insts */
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unsigned div8Latency;
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unsigned div8RepeatRate;
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/** Latency & Repeat Rate for 16-bit Divide Insts */
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unsigned div16Latency;
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unsigned div16RepeatRate;
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/** Latency & Repeat Rate for 24-bit Divide Insts */
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unsigned div24Latency;
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unsigned div24RepeatRate;
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/** Latency & Repeat Rate for 32-bit Divide Insts */
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unsigned div32Latency;
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unsigned div32RepeatRate;
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};
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#endif // _CPU_INORDER_PARAMS_HH__
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