307 lines
8.5 KiB
C++
307 lines
8.5 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_CACHE_UNIT_HH__
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#define __CPU_INORDER_CACHE_UNIT_HH__
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#include <vector>
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#include <list>
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#include <string>
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#include "arch/predecoder.hh"
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#include "arch/tlb.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "mem/port.hh"
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#include "params/InOrderCPU.hh"
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#include "sim/sim_object.hh"
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class CacheRequest;
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typedef CacheRequest* CacheReqPtr;
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class CacheReqPacket;
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typedef CacheReqPacket* CacheReqPktPtr;
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class CacheUnit : public Resource
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{
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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public:
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CacheUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
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virtual ~CacheUnit() {}
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enum Command {
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InitiateFetch,
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CompleteFetch,
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InitiateReadData,
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CompleteReadData,
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InitiateWriteData,
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CompleteWriteData,
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Fetch,
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ReadData,
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WriteData
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};
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public:
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/** CachePort class for the Cache Unit. Handles doing the
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* communication with the cache/memory.
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*/
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class CachePort : public Port
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{
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protected:
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/** Pointer to cache port unit */
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CacheUnit *cachePortUnit;
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public:
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/** Default constructor. */
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CachePort(CacheUnit *_cachePortUnit)
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: Port(_cachePortUnit->name() + "-cache-port",
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(MemObject*)_cachePortUnit->cpu),
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cachePortUnit(_cachePortUnit)
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{ }
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bool snoopRangeSent;
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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/** Functional version of receive. Panics. */
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virtual void recvFunctional(PacketPtr pkt);
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/** Receives status change. Other than range changing, panics. */
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virtual void recvStatusChange(Status status);
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/** Returns the address ranges of this device. */
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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AddrRangeList &snoop)
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{ resp.clear(); snoop.clear(); }
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/** Timing version of receive. Handles setting fetch to the
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* proper status to start fetching. */
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virtual bool recvTiming(PacketPtr pkt);
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/** Handles doing a retry of a failed fetch. */
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virtual void recvRetry();
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};
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enum CachePortStatus {
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cacheWaitResponse,
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cacheWaitRetry,
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cacheAccessComplete
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};
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void init();
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virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num,
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unsigned cmd);
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void requestAgain(DynInstPtr inst, bool &try_request);
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int getSlot(DynInstPtr inst);
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void freeSlot(int slot_num);
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/** Execute the function of this resource. The Default is action
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* is to do nothing. More specific models will derive from this
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* class and define their own execute function.
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*/
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void execute(int slot_num);
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void squash(DynInstPtr inst, int stage_num,
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InstSeqNum squash_seq_num, ThreadID tid);
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/** Processes cache completion event. */
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void processCacheCompletion(PacketPtr pkt);
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void recvRetry();
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/** Align a PC to the start of an I-cache block. */
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Addr cacheBlockAlignPC(Addr addr)
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{
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return (addr & ~(cacheBlkMask));
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}
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/** Returns a specific port. */
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Port *getPort(const std::string &if_name, int idx);
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template <class T>
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Fault read(DynInstPtr inst, Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(DynInstPtr inst, T data, Addr addr, unsigned flags,
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uint64_t *res);
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Fault doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
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int flags, TheISA::TLB::Mode tlb_mode);
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/** Read/Write on behalf of an instruction.
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* curResSlot needs to be a valid value in instruction.
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*/
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Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL);
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void prefetch(DynInstPtr inst);
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void writeHint(DynInstPtr inst);
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uint64_t getMemData(Packet *packet);
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protected:
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/** Cache interface. */
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CachePort *cachePort;
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CachePortStatus cacheStatus;
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CacheReqPtr retryReq;
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PacketPtr retryPkt;
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int retrySlot;
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bool cacheBlocked;
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std::vector<Addr> addrList;
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std::map<Addr, InstSeqNum> addrMap;
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public:
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int cacheBlkSize;
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int cacheBlkMask;
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/** Align a PC to the start of the Cache block. */
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Addr cacheBlockAlign(Addr addr)
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{
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return (addr & ~(cacheBlkMask));
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}
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/** The mem line being fetched. */
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uint8_t *fetchData[ThePipeline::MaxThreads];
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/** @TODO: Move functionaly of fetching more than
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one instruction to 'fetch unit'*/
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/** The Addr of the cacheline that has been loaded. */
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//Addr cacheBlockAddr[ThePipeline::MaxThreads];
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//unsigned fetchOffset[ThePipeline::MaxThreads];
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TheISA::Predecoder predecoder;
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bool tlbBlocked[ThePipeline::MaxThreads];
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TheISA::TLB* tlb();
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TheISA::TLB *_tlb;
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};
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class CacheUnitEvent : public ResourceEvent {
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public:
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const std::string name() const
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{
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return "CacheUnitEvent";
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}
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/** Constructs a resource event. */
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CacheUnitEvent();
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virtual ~CacheUnitEvent() {}
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/** Processes a resource event. */
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virtual void process();
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};
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class CacheRequest : public ResourceRequest
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{
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public:
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CacheRequest(CacheUnit *cres, DynInstPtr inst, int stage_num, int res_idx,
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int slot_num, unsigned cmd, int req_size,
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MemCmd::Command pkt_cmd, unsigned flags, int cpu_id)
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: ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd),
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pktCmd(pkt_cmd), memReq(NULL), reqData(NULL), dataPkt(NULL),
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retryPkt(NULL), memAccComplete(false), memAccPending(false),
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tlbStall(false)
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{ }
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virtual ~CacheRequest()
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{
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if (reqData) {
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delete [] reqData;
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}
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}
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virtual PacketDataPtr getData()
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{ return reqData; }
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void
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setMemAccCompleted(bool completed = true)
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{
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memAccComplete = completed;
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}
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bool isMemAccComplete() { return memAccComplete; }
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void setMemAccPending(bool pending = true) { memAccPending = pending; }
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bool isMemAccPending() { return memAccPending; }
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//Make this data private/protected!
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MemCmd::Command pktCmd;
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RequestPtr memReq;
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PacketDataPtr reqData;
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PacketPtr dataPkt;
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PacketPtr retryPkt;
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bool memAccComplete;
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bool memAccPending;
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bool tlbStall;
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};
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class CacheReqPacket : public Packet
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{
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public:
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CacheReqPacket(CacheRequest *_req,
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Command _cmd, short _dest)
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: Packet(_req->memReq, _cmd, _dest), cacheReq(_req)
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{
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}
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CacheRequest *cacheReq;
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};
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#endif //__CPU_CACHE_UNIT_HH__
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