151 lines
4.9 KiB
C++
151 lines
4.9 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/branch_predictor.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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BranchPredictor::BranchPredictor(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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branchPred(params)
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{
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instSize = sizeof(MachInst);
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}
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void
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BranchPredictor::regStats()
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{
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predictedTaken
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.name(name() + ".predictedTaken")
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.desc("Number of Branches Predicted As Taken (True).");
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predictedNotTaken
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.name(name() + ".predictedNotTaken")
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.desc("Number of Branches Predicted As Not Taken (False).");
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Resource::regStats();
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}
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void
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BranchPredictor::execute(int slot_num)
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{
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// After this is working, change this to a reinterpret cast
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// for performance considerations
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ResourceRequest* bpred_req = reqMap[slot_num];
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DynInstPtr inst = bpred_req->inst;
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ThreadID tid = inst->readTid();
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int seq_num = inst->seqNum;
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//int stage_num = bpred_req->getStageNum();
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bpred_req->fault = NoFault;
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switch (bpred_req->cmd)
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{
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case PredictBranch:
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{
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Addr pred_PC = inst->readNextPC();
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if (inst->isControl()) {
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// If not, the pred_PC be updated to pc+8
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// If predicted, the pred_PC will be updated to new target value
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bool predict_taken = branchPred.predict(inst, pred_PC, tid);
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if (predict_taken) {
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DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted true.\n",
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tid, seq_num);
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inst->setPredTarg(pred_PC);
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predictedTaken++;
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} else {
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DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Branch predicted false.\n",
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tid, seq_num);
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if (inst->isCondDelaySlot())
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{
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inst->setPredTarg(inst->readPC() + (2 * instSize));
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} else {
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inst->setPredTarg(pred_PC);
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}
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predictedNotTaken++;
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}
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inst->setBranchPred(predict_taken);
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DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is %08p.\n",
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tid, seq_num, pred_PC);
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} else {
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DPRINTF(InOrderBPred, "[tid:%i]: Ignoring [sn:%i] because this isn't "
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"a control instruction.\n", tid, seq_num);
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}
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bpred_req->done();
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}
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break;
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case UpdatePredictor:
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{
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DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Updating Branch Predictor.\n",
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tid, seq_num);
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branchPred.update(seq_num, tid);
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bpred_req->done();
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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void
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BranchPredictor::squash(DynInstPtr inst, int squash_stage,
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InstSeqNum squash_seq_num, ThreadID tid)
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{
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DPRINTF(InOrderBPred, "Squashing...\n");
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branchPred.squash(squash_seq_num, tid);
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}
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void
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BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
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{
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branchPred.update(seq_num, tid);
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}
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