d9c3b636b0
--HG-- rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/config.ini => tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/config.out => tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.msg => tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/smred.out => tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr rename : tests/long/50.vortex/ref/alpha/linux/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.msg => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/smred.out => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr rename : tests/long/50.vortex/ref/alpha/linux/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini => tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out => tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.msg => tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/smred.out => tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr rename : tests/long/50.vortex/ref/alpha/linux/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout extra : convert_revision : b62b8949628327d0a0ed2971772aa4f848764d54
90 lines
1.4 KiB
INI
90 lines
1.4 KiB
INI
[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[serialize]
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count=10
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cycle=0
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dir=cpt.%012d
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period=0
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[stats]
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descriptions=true
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dump_cycle=0
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dump_period=0
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dump_reset=false
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ignore_events=
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mysql_db=
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mysql_host=
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mysql_password=
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mysql_user=
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_compat=true
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text_file=m5stats.txt
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=workload
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clock=1
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cpu_id=0
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defer_registration=false
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function_trace=false
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function_trace_start=0
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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phase=0
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progress_interval=0
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simulate_stalls=false
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system=system
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.port[2]
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icache_port=system.membus.port[1]
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[system.cpu.workload]
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type=LiveProcess
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cmd=vortex lendian.raw
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cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
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egid=100
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env=
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euid=100
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executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
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gid=100
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input=cin
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output=cout
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pid=100
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ppid=99
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system=system
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uid=100
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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responder_set=false
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width=64
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port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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