6c88730540
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
408 lines
12 KiB
C++
408 lines
12 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_RESOURCE_HH__
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#define __CPU_INORDER_RESOURCE_HH__
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#include <vector>
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#include <list>
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#include <string>
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#include "cpu/inst_seq.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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class Event;
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class InOrderCPU;
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class ResourceEvent;
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class ResourceRequest;
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typedef ResourceRequest ResReq;
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typedef ResourceRequest* ResReqPtr;
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class Resource {
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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friend class ResourceEvent;
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friend class ResourceRequest;
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public:
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Resource(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu);
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virtual ~Resource();
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/** Return name of this resource */
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virtual std::string name();
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/** Define this function if resource, has a port to connect to an outside
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* simulation object.
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*/
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virtual Port* getPort(const std::string &if_name, int idx) { return NULL; }
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/** Return ID for this resource */
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int getId() { return id; }
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/** Any extra initiliazation stuff can be set up using this function that
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* should get called before the simulation starts (tick 0)
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*/
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virtual void init();
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virtual void initSlots();
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/** Register Stats for this resource */
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virtual void regStats();
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/** Resources that care about thread activation override this. */
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virtual void activateThread(unsigned tid) { }
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/** Deactivate Thread. Default action is to squash all instructions
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* from deactivated thread.
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*/
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virtual void deactivateThread(unsigned tid);
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/** Resources that care when an instruction has been graduated
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* can override this
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*/
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virtual void instGraduated(InstSeqNum seq_num,unsigned tid) { }
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/** Request usage of this resource. Returns a ResourceRequest object
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* with all the necessary resource information
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*/
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virtual ResourceRequest* request(DynInstPtr inst);
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/** Get the next available slot in this resource. Instruction is passed
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* so that resources can check the instruction before allocating a slot
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* if necessary.
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*/
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virtual int getSlot(DynInstPtr inst);
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/** Find the slot that this instruction is using in a resource */
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virtual int findSlot(DynInstPtr inst);
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/** Free a resource slot */
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virtual void freeSlot(int slot_idx);
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/** Request usage of a resource for this instruction. If this instruction already
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* has made this request to this resource, and that request is uncompleted
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* this function will just return that request
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*/
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virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num,
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unsigned cmd);
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/** Schedule Execution of This Resource For A Given Slot*/
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virtual void scheduleExecution(int slot_idx);
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/** Execute the function of this resource. The Default is action
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* is to do nothing. More specific models will derive from this
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* class and define their own execute function.
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*/
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virtual void execute(int slot_idx);
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/** Fetch on behalf of an instruction. Will check to see
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* if instruction is actually in resource before
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* trying to fetch. Needs to be defined for derived units.
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*/
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virtual Fault doFetchAccess(DynInstPtr inst)
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{ panic("doFetchAccess undefined for %s", name()); return NoFault; }
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/** Read/Write on behalf of an instruction. Will check to see
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* if instruction is actually in resource before
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* trying to do access.Needs to be defined for derived units.
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*/
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virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
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{ panic("doCacheAccess undefined for %s", name()); return NoFault; }
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virtual void prefetch(DynInstPtr inst)
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{ panic("prefetch undefined for %s", name()); }
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virtual void writeHint(DynInstPtr inst)
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{ panic("writeHint undefined for %s", name()); }
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/** Squash All Requests After This Seq Num */
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virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
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/** The number of instructions available that this resource can
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* can still process
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*/
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int slotsAvail();
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/** The number of instructions using this resource */
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int slotsInUse();
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/** Schedule resource event, regardless of its current state. */
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void scheduleEvent(int slot_idx, int delay);
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/** Find instruction in list, Schedule resource event, regardless of its current state. */
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bool scheduleEvent(DynInstPtr inst, int delay);
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/** Unschedule resource event, regardless of its current state. */
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void unscheduleEvent(int slot_idx);
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/** Unschedule resource event, regardless of its current state. */
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bool unscheduleEvent(DynInstPtr inst);
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/** Return the number of cycles in 'Tick' format */
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Tick ticks(int numCycles);
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/** Find the request that corresponds to this instruction */
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virtual ResReqPtr findRequest(DynInstPtr inst);
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/** */
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virtual void rejectRequest(DynInstPtr inst);
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/** Request a Resource again. Some resources have to special process this
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* in subsequent accesses.
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*/
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virtual void requestAgain(DynInstPtr inst, bool &try_request);
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/** Return Latency of Resource */
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/* Can be overridden for complex cases */
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virtual int getLatency(int slot_num) { return latency; }
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protected:
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/** The name of this resource */
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std::string resName;
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/** ID of the resource. The Resource Pool uses this # to identify this
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* resource.
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*/
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int id;
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/** The number of instructions the resource can simultaneously
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* process.
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*/
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int width;
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/** Constant latency for this resource.
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* Note: Dynamic latency resources set this to 0 and
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* manage the latency themselves
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*/
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const int latency;
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public:
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/** Mapping of slot-numbers to the resource-request pointers */
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std::map<int, ResReqPtr> reqMap;
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/** A list of all the available execution slots for this resource.
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* This correlates with the actual resource event idx.
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*/
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std::vector<int> availSlots;
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/** The CPU(s) that this resource interacts with */
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InOrderCPU *cpu;
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protected:
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/** The resource event used for scheduling resource slots on the
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* event queue
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*/
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ResourceEvent *resourceEvent;
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/** Default denied resource request pointer*/
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ResReqPtr deniedReq;
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public:
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/////////////////////////////////////////////////////////////////
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//
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// DEFAULT RESOURCE STATISTICS
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//
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/////////////////////////////////////////////////////////////////
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/** Number of Instruction Requests the Resource Processes */
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Stats::Scalar instReqsProcessed;
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};
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class ResourceEvent : public Event
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{
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public:
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/** Pointer to the CPU. */
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Resource *resource;
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/// Resource events that come before other associated CPU events
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/// (for InOrderCPU model).
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/// check src/sim/eventq.hh for more event priorities.
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enum InOrderPriority {
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Resource_Event_Pri = 45,
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};
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/** The Resource Slot that this event is servicing */
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int slotIdx;
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/** Constructs a resource event. */
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ResourceEvent();
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ResourceEvent(Resource *res, int slot_idx);
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virtual ~ResourceEvent() { }
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/** Initialize data for this resource event. */
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virtual void init(Resource *res, int slot_idx);
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/** Processes a resource event. */
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virtual void process();
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/** Returns the description of the resource event. */
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const char *description();
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/** Set slot idx for event */
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void setSlot(int slot) { slotIdx = slot; }
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/** Schedule resource event, regardless of its current state. */
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void scheduleEvent(int delay)
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{
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if (squashed())
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mainEventQueue.reschedule(this, curTick + resource->ticks(delay));
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else if (!scheduled())
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mainEventQueue.schedule(this, curTick + resource->ticks(delay));
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}
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/** Unschedule resource event, regardless of its current state. */
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void unscheduleEvent()
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{
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if (scheduled())
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squash();
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}
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};
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class ResourceRequest
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{
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public:
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typedef ThePipeline::DynInstPtr DynInstPtr;
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static int resReqID;
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static int resReqCount;
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public:
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ResourceRequest(Resource *_res, DynInstPtr _inst, int stage_num,
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int res_idx, int slot_num, unsigned _cmd)
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: res(_res), inst(_inst), cmd(_cmd), stageNum(stage_num),
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resIdx(res_idx), slotNum(slot_num), completed(false),
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squashed(false), processing(false), waiting(false)
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{
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reqID = resReqID++;
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resReqCount++;
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DPRINTF(ResReqCount, "Res. Req %i created. resReqCount=%i.\n", reqID, resReqCount);
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if (resReqCount > 100) {
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fatal("Too many undeleted resource requests. Memory leak?\n");
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}
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}
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virtual ~ResourceRequest()
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{
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resReqCount--;
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DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID, resReqCount);
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}
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int reqID;
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/** Acknowledge that this is a request is done and remove
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* from resource.
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*/
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void done(bool completed = true);
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/////////////////////////////////////////////
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//
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// GET RESOURCE REQUEST IDENTIFICATION / INFO
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//
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/////////////////////////////////////////////
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/** Get Resource Index */
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int getResIdx() { return resIdx; }
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/** Get Slot Number */
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int getSlot() { return slotNum; }
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/** Get Stage Number */
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int getStageNum() { return stageNum; }
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/** Set/Get Thread Ids */
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void setTid(unsigned _tid) { tid = _tid; }
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int getTid() { return tid; }
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/** Instruction this request is for */
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DynInstPtr getInst() { return inst; }
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/** Data from this request. Overridden by Resource-Specific Request
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* Objects
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*/
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virtual PacketDataPtr getData() { return NULL; }
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/** Pointer to Resource that is being used */
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Resource *res;
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/** Instruction being used */
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DynInstPtr inst;
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/** Fault Associated With This Resource Request */
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Fault fault;
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/** Command For This Resource */
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unsigned cmd;
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////////////////////////////////////////
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//
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// GET RESOURCE REQUEST STATUS FROM VARIABLES
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//
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////////////////////////////////////////
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/** Get/Set Completed variables */
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bool isCompleted() { return completed; }
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void setCompleted(bool cond = true) { completed = cond; }
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/** Get/Set Squashed variables */
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bool isSquashed() { return squashed; }
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void setSquashed() { squashed = true; }
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/** Get/Set IsProcessing variables */
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bool isProcessing() { return processing; }
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void setProcessing() { processing = true; }
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/** Get/Set IsWaiting variables */
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bool isWaiting() { return waiting; }
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void setWaiting() { waiting = true; }
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protected:
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/** Resource Identification */
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int tid;
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int stageNum;
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int resIdx;
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int slotNum;
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/** Resource Status */
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bool completed;
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bool squashed;
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bool processing;
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bool waiting;
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};
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#endif //__CPU_INORDER_RESOURCE_HH__
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