127 lines
3.9 KiB
C++
Executable file
127 lines
3.9 KiB
C++
Executable file
/*
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* Copyright (c) 2002, 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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*/
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#include "arch/mips/faults.hh"
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/tlb.hh"
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//#include "base/kgdb.h"
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#include "base/remote_gdb.hh"
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#include "base/stats/events.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/debug.hh"
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#include "sim/sim_exit.hh"
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#include "arch/mips/mips_core_specific.hh"
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#if FULL_SYSTEM
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////////////////////////////////////////////////////////////////////////
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//
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// Machine dependent functions
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//
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void
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MipsISA::initCPU(ThreadContext *tc, int cpuId)
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{
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// MipsFault *reset = new ResetFault;
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// tc->setPC(reset->vect());
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// tc->setNextPC(tc->readPC() + sizeof(MachInst));
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// delete reset;
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}
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template <class CPU>
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void
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MipsISA::processInterrupts(CPU *cpu)
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{
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//Check if there are any outstanding interrupts
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//Handle the interrupts
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/* int ipl = 0;
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int summary = 0;
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cpu->checkInterrupts = false;
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if (cpu->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (cpu->readMiscReg(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = cpu->intr_status();
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if (interrupts) {
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
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cpu->setMiscReg(IPR_ISR, summary);
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cpu->setMiscReg(IPR_INTID, ipl);
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cpu->trap(new InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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cpu->readMiscReg(IPR_IPLR), ipl, summary);
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}
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*/
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}
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/*int
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MipsISA::MiscRegFile::getInstAsid()
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{
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return AlphaISA::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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}
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int
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MipsISA::MiscRegFile::getDataAsid()
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{
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return AlphaISA::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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}*/
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#endif // FULL_SYSTEM || BARE_IRON
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