386 lines
11 KiB
C++
386 lines
11 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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* Jaidev Patwardhan
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/mips_core_specific.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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namespace LittleEndianGuest {};
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#define TARGET_MIPS
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class StaticInstPtr;
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namespace MipsISA
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{
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using namespace LittleEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// MIPS DOES have a delay slot
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#define ISA_HAS_DELAY_SLOT 1
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const Addr PageShift = 13;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr Page_Mask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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const Addr PteShift = 3;
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const Addr NPtePageShift = PageShift - PteShift;
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const Addr NPtePage = ULL(1) << NPtePageShift;
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const Addr PteMask = NPtePage - 1;
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//// All 'Mapped' segments go through the TLB
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//// All other segments are translated by dropping the MSB, to give
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//// the corresponding physical address
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// User Segment - Mapped
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const Addr USegBase = ULL(0x0);
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const Addr USegEnd = ULL(0x7FFFFFFF);
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// Kernel Segment 0 - Unmapped
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const Addr KSeg0End = ULL(0x9FFFFFFF);
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const Addr KSeg0Base = ULL(0x80000000);
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const Addr KSeg0Mask = ULL(0x1FFFFFFF);
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// Kernel Segment 1 - Unmapped, Uncached
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const Addr KSeg1End = ULL(0xBFFFFFFF);
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const Addr KSeg1Base = ULL(0xA0000000);
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const Addr KSeg1Mask = ULL(0x1FFFFFFF);
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// Kernel/Supervisor Segment - Mapped
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const Addr KSSegEnd = ULL(0xDFFFFFFF);
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const Addr KSSegBase = ULL(0xC0000000);
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// Kernel Segment 3 - Mapped
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const Addr KSeg3End = ULL(0xFFFFFFFF);
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const Addr KSeg3Base = ULL(0xE0000000);
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// For loading... XXX This maybe could be USegEnd?? --ali
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const Addr LoadAddrMask = ULL(0xffffffffff);
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inline Addr Phys2K0Seg(Addr addr)
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{
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// if (addr & PAddrUncachedBit43) {
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// addr &= PAddrUncachedMask;
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// addr |= PAddrUncachedBit40;
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// }
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return addr | KSeg0Base;
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}
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const unsigned VABits = 32;
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const unsigned PABits = 32; // Is this correct?
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const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
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const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
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////////////////////////////////////////////////////////////////////////
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//
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// Interrupt levels
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//
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enum InterruptLevels
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{
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INTLEVEL_SOFTWARE_MIN = 4,
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INTLEVEL_SOFTWARE_MAX = 19,
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INTLEVEL_EXTERNAL_MIN = 20,
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INTLEVEL_EXTERNAL_MAX = 34,
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INTLEVEL_IRQ0 = 20,
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INTLEVEL_IRQ1 = 21,
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INTINDEX_ETHERNET = 0,
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INTINDEX_SCSI = 1,
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INTLEVEL_IRQ2 = 22,
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INTLEVEL_IRQ3 = 23,
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INTLEVEL_SERIAL = 33,
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NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
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};
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// MIPS modes
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enum mode_type
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{
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mode_kernel = 0, // kernel
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mode_supervisor = 1, // supervisor
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mode_user = 2, // user mode
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mode_debug = 3, // debug mode
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mode_number // number of modes
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};
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inline mode_type getOperatingMode(MiscReg Stat)
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{
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if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
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return mode_kernel;
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else{
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if((Stat & 0x18) == 0x8)
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return mode_supervisor;
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else if((Stat & 0x18) == 0x10)
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return mode_user;
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else return mode_number;
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}
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}
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// return a no-op instruction... used for instruction fetch faults
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const ExtMachInst NoopMachInst = 0x00000000;
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// Constants Related to the number of registers
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const int NumIntArchRegs = 32;
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const int NumIntSpecialRegs = 9;
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const int NumFloatArchRegs = 32;
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const int NumFloatSpecialRegs = 5;
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const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
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const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
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const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
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// Static instruction parameters
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const int MaxInstSrcRegs = 10;
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const int MaxInstDestRegs = 8;
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// semantically meaningful register indices
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const int ZeroReg = 0;
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const int AssemblerReg = 1;
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const int SyscallSuccessReg = 7;
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const int FirstArgumentReg = 4;
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const int ReturnValueReg = 2;
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const int KernelReg0 = 26;
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const int KernelReg1 = 27;
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const int GlobalPointerReg = 28;
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const int StackPointerReg = 29;
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const int FramePointerReg = 30;
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const int ReturnAddressReg = 31;
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const int SyscallPseudoReturnReg = 3;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int MachineBytes = 4;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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const int ANNOTE_NONE = 0;
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const uint32_t ITOUCH_ANNOTE = 0xffffffff;
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// These help enumerate all the registers for dependence tracking.
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const int FP_Base_DepTag = NumIntRegs;
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const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
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// Enumerate names for 'Control' Registers in the CPU
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// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
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// (Register Number-Register Select) Summary of Register
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//------------------------------------------------------
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// The first set of names classify the CP0 names as Register Banks
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// for easy indexing when using the 'RD + SEL' index combination
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// in CP0 instructions.
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enum MiscRegTags {
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Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3
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MVPControl,
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MVPConf0,
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MVPConf1,
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CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15
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VPEControl,
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VPEConf0,
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VPEConf1,
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YQMask,
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VPESchedule,
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VPEScheFBack,
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VPEOpt,
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EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23
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TCStatus,
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TCBind,
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TCRestart,
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TCHalt,
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TCContext,
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TCSchedule,
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TCScheFBack,
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EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24
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Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33
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ContextConfig,
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PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
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PageGrain = Ctrl_Base_DepTag + 41,
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Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55
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SRSConf0,
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SRSConf1,
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SRSConf2,
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SRSConf3,
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SRSConf4,
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HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63
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BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71
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Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79
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EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87
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Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95
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Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103
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IntCtl,
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SRSCtl,
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SRSMap,
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Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111
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EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119
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PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127,
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EBase,
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Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135
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Config1,
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Config2,
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Config3,
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Config4,
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Config5,
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Config6,
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Config7,
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LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143
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WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151
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WatchLo1,
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WatchLo2,
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WatchLo3,
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WatchLo4,
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WatchLo5,
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WatchLo6,
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WatchLo7,
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WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159
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WatchHi1,
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WatchHi2,
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WatchHi3,
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WatchHi4,
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WatchHi5,
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WatchHi6,
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WatchHi7,
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XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
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//Bank 21: 168-175
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//Bank 22: 176-183
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Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191
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TraceControl1,
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TraceControl2,
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UserTraceData,
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TraceBPC,
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DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199
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PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207
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PerfCnt1,
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PerfCnt2,
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PerfCnt3,
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PerfCnt4,
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PerfCnt5,
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PerfCnt6,
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PerfCnt7,
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ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215
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CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223
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CacheErr1,
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CacheErr2,
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CacheErr3,
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TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231
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DataLo1,
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TagLo2,
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DataLo3,
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TagLo4,
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DataLo5,
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TagLo6,
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DataLo7,
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TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239
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DataHi1,
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TagHi2,
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DataHi3,
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TagHi4,
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DataHi5,
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TagHi6,
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DataHi7,
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ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247
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DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256
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LLFlag = Ctrl_Base_DepTag + 257,
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NumControlRegs
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};
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const int TotalDataRegs = NumIntRegs + NumFloatRegs;
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const int NumMiscRegs = NumControlRegs;
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const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
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};
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#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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