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gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
sim_ticks 21947000 # Number of ticks simulated
final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 95577 # Simulator instruction rate (inst/s)
host_op_rate 95558 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 329070081 # Simulator tick rate (ticks/s)
host_mem_usage 294868 # Number of bytes of host memory used
host_seconds 0.07 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
system.physmem.bytes_read::total 31104 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 486 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 69 # Per bank write bursts
system.physmem.perBankRdBursts::1 33 # Per bank write bursts
system.physmem.perBankRdBursts::2 32 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdBursts::4 42 # Per bank write bursts
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdBursts::10 22 # Per bank write bursts
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdBursts::12 14 # Per bank write bursts
system.physmem.perBankRdBursts::13 120 # Per bank write bursts
system.physmem.perBankRdBursts::14 45 # Per bank write bursts
system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 21815000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 486 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation
system.physmem.totQLat 4379250 # Total ticks spent queuing
system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 11.07 # Data bus utilization in percentage
system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 390 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 44886.83 # Average gap between requests
system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ)
system.physmem_0.averagePower 873.750829 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ)
system.physmem_1.averagePower 854.849834 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 2810 # Number of BP lookups
system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups
system.cpu.branchPred.BTBHits 679 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 2105 # DTB read hits
system.cpu.dtb.read_misses 55 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 2160 # DTB read accesses
system.cpu.dtb.write_hits 1074 # DTB write hits
system.cpu.dtb.write_misses 30 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 1104 # DTB write accesses
system.cpu.dtb.data_hits 3179 # DTB hits
system.cpu.dtb.data_misses 85 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 3264 # DTB accesses
system.cpu.itb.fetch_hits 2194 # ITB hits
system.cpu.itb.fetch_misses 34 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2228 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 43895 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 2414 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 2425 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 10735 # Type of FU issued
system.cpu.iq.rate 0.244561 # Inst issue rate
system.cpu.iq.fu_busy_cnt 144 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 86 # number of nop insts executed
system.cpu.iew.exec_refs 3269 # number of memory reference insts executed
system.cpu.iew.exec_branches 1598 # Number of branches executed
system.cpu.iew.exec_stores 1106 # Number of stores executed
system.cpu.iew.exec_rate 0.233330 # Inst execution rate
system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 9794 # cumulative count of insts written-back
system.cpu.iew.wb_producers 5300 # num instructions producing a value
system.cpu.iew.wb_consumers 7297 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2048 # Number of memory references committed
system.cpu.commit.loads 1183 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 1050 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 25490 # The number of ROB reads
system.cpu.rob.rob_writes 27321 # The number of ROB writes
system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction
system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads
system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 13013 # number of integer regfile reads
system.cpu.int_regfile_writes 7460 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits
system.cpu.dcache.overall_hits::total 2343 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses
system.cpu.dcache.overall_misses::total 516 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4702 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits
system.cpu.icache.overall_hits::total 1714 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses
system.cpu.icache.overall_misses::total 480 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2194 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2194 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2194 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2194 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2194 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218778 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.218778 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.218778 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.218778 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.218778 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.218778 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 69946.875000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 69946.875000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24137500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 24137500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24137500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 24137500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24137500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 24137500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143118 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143118 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143118 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76871.019108 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76871.019108 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76871.019108 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76871.019108 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76871.019108 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76871.019108 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 218.935718 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.272937 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 60.662780 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004830 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001851 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006681 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 313 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 313 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses
system.cpu.l2cache.overall_misses::total 486 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5800000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5800000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23655000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 23655000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8428500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8428500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 23655000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 14228500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 37883500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 23655000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 14228500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 37883500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 314 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 314 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996815 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80555.555556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80555.555556 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75575.079872 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75575.079872 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83450.495050 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83450.495050 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77949.588477 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77949.588477 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 313 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 313 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5080000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20525000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20525000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7418500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7418500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20525000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12498500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 33023500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20525000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12498500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 33023500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996815 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
system.membus.trans_dist::ReadResp 414 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 486 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 486 # Request fanout histogram
system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
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