1242 lines
143 KiB
Plaintext
1242 lines
143 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.410670 # Number of seconds simulated
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sim_ticks 410669815000 # Number of ticks simulated
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final_tick 410669815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 94058 # Simulator instruction rate (inst/s)
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host_op_rate 115798 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 60293323 # Simulator tick rate (ticks/s)
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host_mem_usage 320128 # Number of bytes of host memory used
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host_seconds 6811.20 # Real time elapsed on the host
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sim_insts 640649299 # Number of instructions simulated
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sim_ops 788724958 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 232448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7026304 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 12953152 # Number of bytes read from this memory
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system.physmem.bytes_read::total 20211904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 232448 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 232448 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4244928 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4244928 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3632 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 109786 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 202393 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 315811 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66327 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66327 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 566022 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 17109375 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 31541524 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 49216921 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 566022 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 566022 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 10336596 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 10336596 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 10336596 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 566022 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 17109375 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 31541524 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 59553517 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 315811 # Number of read requests accepted
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system.physmem.writeReqs 66327 # Number of write requests accepted
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system.physmem.readBursts 315811 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66327 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 20192576 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4239424 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 20211904 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4244928 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 58 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 19865 # Per bank write bursts
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system.physmem.perBankRdBursts::1 19533 # Per bank write bursts
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system.physmem.perBankRdBursts::2 19787 # Per bank write bursts
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system.physmem.perBankRdBursts::3 19881 # Per bank write bursts
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system.physmem.perBankRdBursts::4 19767 # Per bank write bursts
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system.physmem.perBankRdBursts::5 20312 # Per bank write bursts
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system.physmem.perBankRdBursts::6 19558 # Per bank write bursts
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system.physmem.perBankRdBursts::7 19499 # Per bank write bursts
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system.physmem.perBankRdBursts::8 19473 # Per bank write bursts
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system.physmem.perBankRdBursts::9 19475 # Per bank write bursts
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system.physmem.perBankRdBursts::10 19453 # Per bank write bursts
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system.physmem.perBankRdBursts::11 19704 # Per bank write bursts
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system.physmem.perBankRdBursts::12 19596 # Per bank write bursts
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system.physmem.perBankRdBursts::13 20052 # Per bank write bursts
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system.physmem.perBankRdBursts::14 19574 # Per bank write bursts
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system.physmem.perBankRdBursts::15 19980 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4265 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4106 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4140 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4153 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4250 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4230 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4095 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4093 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4156 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 410669760500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 315811 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66327 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 122285 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 120755 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 14364 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6416 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 7563 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 8652 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 9282 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 3822 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 2905 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 2145 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1570 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 942 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 987 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 1782 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3801 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4170 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4413 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4689 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4948 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5154 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5054 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4960 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4217 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4099 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 91 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 89 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 88 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 82 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 102 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 80 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 54 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 48 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 136666 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 178.756150 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 128.878617 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 198.405742 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 53923 39.46% 39.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 57606 42.15% 81.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 14740 10.79% 92.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1412 1.03% 93.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1397 1.02% 94.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1387 1.01% 95.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1267 0.93% 96.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1142 0.84% 97.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3792 2.77% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 136666 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4031 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 73.293227 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 34.720611 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 661.085009 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4010 99.48% 99.48% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 10 0.25% 99.73% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::2048-3071 2 0.05% 99.78% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.88% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::9216-10239 1 0.02% 99.90% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::11264-12287 1 0.02% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::19456-20479 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::26624-27647 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4031 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 4031 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.432895 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.394232 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.238105 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3399 84.32% 84.32% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::17 3 0.07% 84.40% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::18 453 11.24% 95.63% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::19 84 2.08% 97.72% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::20 29 0.72% 98.44% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::21 17 0.42% 98.86% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22 10 0.25% 99.11% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::23 13 0.32% 99.43% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::24 10 0.25% 99.68% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26 3 0.07% 99.80% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::27 2 0.05% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 1 0.02% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 3 0.07% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::total 4031 # Writes before turning the bus around for reads
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system.physmem.totQLat 8703208249 # Total ticks spent queuing
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system.physmem.totMemAccLat 14619001999 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1577545000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 27584.66 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 46334.66 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 49.17 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 49.22 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 10.34 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.46 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.17 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 218486 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 26585 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 69.25 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 40.12 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 1074663.50 # Average gap between requests
|
|
system.physmem.pageHitRate 64.19 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 519334200 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 283366875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1233694800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 96824469870 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 161463849000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 287363708985 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 699.756123 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 267972811336 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 13712920000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 128976939914 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 513679320 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 280281375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1226604600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 212718960 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 96486689295 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 161760147750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 287302592820 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 699.607300 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 268468666587 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 13712920000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 128482733413 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 234660907 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 161885632 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15514558 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 122787051 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 109471469 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 89.155549 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 25674321 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1300177 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 673 # Number of system calls
|
|
system.cpu.numCycles 821339631 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 85359172 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 1200831144 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 234660907 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 135145790 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 720108706 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 31063537 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 2772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 3327 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 371279487 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 652622 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 821005776 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.826136 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.165203 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 139284134 16.97% 16.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 223266821 27.19% 44.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 99362992 12.10% 56.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 359091829 43.74% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 821005776 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.285705 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.462040 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 121274951 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 160921163 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 484660075 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 38631496 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 15518091 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 25119096 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 1248135517 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 39967011 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 15518091 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 178281745 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 80150846 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 211317 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 464319561 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 82524216 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 1190646555 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 25420306 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 24957441 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2267221 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 41531798 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1705173 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 1225452951 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 5812557102 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1358174955 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 40876459 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 350674721 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 108777970 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 366242931 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 236095379 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1613389 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 5371796 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 1168681315 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1017114082 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 18565562 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 379968716 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1032836656 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 821005776 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.238863 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.084756 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 263349245 32.08% 32.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 227125536 27.66% 59.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 217733280 26.52% 86.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 96668881 11.77% 98.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 16128827 1.96% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 821005776 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 63875016 18.90% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 18146 0.01% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.90% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 157510134 46.60% 65.69% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 115986364 34.31% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 456370249 44.87% 44.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 5195831 0.51% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 322123387 31.67% 78.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 215570268 21.19% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1017114082 # Type of FU issued
|
|
system.cpu.iq.rate 1.238360 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 338026549 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.332339 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 3149949023 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 1505114950 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 934262178 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 61877028 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 43565833 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1321330304 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 33810327 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 9960611 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 114001993 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18396 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 107114883 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2065819 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 19975 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 15518091 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 35326945 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 43224 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1168699230 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 366242931 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 236095379 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 46833 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18396 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 15437302 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3784553 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19221855 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 974739392 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 303297512 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 42374690 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 5556 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 497752889 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 150613606 # Number of branches executed
|
|
system.cpu.iew.exec_stores 194455377 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.186768 # Inst execution rate
|
|
system.cpu.iew.wb_sent 963712681 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 960414622 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 536046271 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 893280305 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.169327 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.600087 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 357416983 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 770184473 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.024079 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.777435 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 431571304 56.03% 56.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 174376243 22.64% 78.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 72936565 9.47% 88.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 32893073 4.27% 92.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 8539337 1.11% 93.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 14258396 1.85% 95.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 7274917 0.94% 96.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 5974456 0.78% 97.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 22360182 2.90% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 770184473 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 640654411 # Number of instructions committed
|
|
system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 381221434 # Number of memory references committed
|
|
system.cpu.commit.loads 252240938 # Number of loads committed
|
|
system.cpu.commit.membars 5740 # Number of memory barriers committed
|
|
system.cpu.commit.branches 137364860 # Number of branches committed
|
|
system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 19275340 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 22360182 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1893962593 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 2343119332 # The number of ROB writes
|
|
system.cpu.timesIdled 647411 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 333855 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 640649299 # Number of Instructions Simulated
|
|
system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.282043 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.282043 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.780005 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.780005 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 995778090 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 567907785 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 3794401386 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 384898061 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 715805814 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2756185 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.933524 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 414216512 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 150.258266 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 256787000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.933524 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999870 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 839346679 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 839346679 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 286293684 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 286293684 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 127908123 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 127908123 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 414201807 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 414201807 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 414204964 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 414204964 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 3034548 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 3034548 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1043354 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1043354 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 4077902 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4077902 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 4078548 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4078548 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35018337000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 35018337000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10025314350 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 10025314350 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 45043651350 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 45043651350 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 45043651350 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 45043651350 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 289328232 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 289328232 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 418279709 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 418279709 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 418283512 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 418283512 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008091 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.008091 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009749 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009749 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009751 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009751 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9608.737159 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 9608.737159 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 11045.790544 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 11044.041004 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 356457 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 4730 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 75.360888 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 735102 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 735102 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999338 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 999338 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322490 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 322490 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1321828 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1321828 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1321828 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1321828 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035210 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2035210 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23819094000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23819094000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959479350 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959479350 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6004500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6004500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29778573350 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 29778573350 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29784577850 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 29784577850 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11703.506763 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11703.506763 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8267.134092 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8267.134092 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9367.394696 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9367.394696 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10804.707475 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10804.707475 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10804.373267 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10804.373267 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 5169482 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.670586 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 366104789 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 5169992 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 70.813415 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 247000500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.670586 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997403 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997403 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 326 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 747728920 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 747728920 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 366104823 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 366104823 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 366104823 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 366104823 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 366104823 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 366104823 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5174632 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5174632 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5174632 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5174632 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5174632 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5174632 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647292422 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 41647292422 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 41647292422 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 41647292422 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 41647292422 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 41647292422 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 371279455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 371279455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 371279455 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 371279455 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 371279455 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 371279455 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013937 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013937 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013937 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.013937 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013937 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.013937 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.358303 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8048.358303 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8048.358303 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8048.358303 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 80051 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 126 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3834 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.879238 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 25.200000 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4621 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 4621 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 4621 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 4621 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 4621 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 4621 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170011 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 5170011 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 5170011 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 5170011 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 5170011 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 5170011 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39018363435 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 39018363435 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39018363435 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 39018363435 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39018363435 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 39018363435 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013925 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013925 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013925 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013925 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013925 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013925 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7547.056174 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7547.056174 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7547.056174 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 7547.056174 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7547.056174 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 7547.056174 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 1350243 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 1354972 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 4137 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 4790004 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 299528 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16361.547684 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 14361788 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 315892 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 45.464235 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 13446572000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 726.373597 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.641683 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 8786.659313 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6719.873092 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.044334 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007852 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.536295 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410149 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 6547 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 9817 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 156 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1466 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4910 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 236 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2098 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7222 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.399597 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599182 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 244366339 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 244366339 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 735102 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 735102 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 718398 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 718398 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5166353 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 5166353 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1926489 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1926489 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5166353 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2644887 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7811240 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5166353 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2644887 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7811240 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2448 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2448 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3641 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 3641 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 109362 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 109362 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3641 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 111810 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 115451 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3641 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 111810 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 115451 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 205155000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 205155000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 266848500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 266848500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8243205000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8243205000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 266848500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8448360000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8715208500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 266848500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8448360000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8715208500 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 735102 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 735102 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169994 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 5169994 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035851 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 2035851 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 5169994 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2756697 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 7926691 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 5169994 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2756697 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 7926691 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003396 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003396 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000704 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000704 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.053718 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.053718 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000704 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.040559 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014565 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000704 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.040559 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014565 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1277.777778 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1277.777778 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83805.147059 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83805.147059 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73289.892887 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73289.892887 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75375.404620 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75375.404620 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73289.892887 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75559.967803 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 75488.376021 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73289.892887 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75559.967803 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 75488.376021 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66327 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66327 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1069 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1069 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 955 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 955 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 2024 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 2033 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 2024 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 2033 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8960 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 8960 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202470 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 202470 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1379 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1379 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3632 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3632 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108407 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108407 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3632 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 109786 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 113418 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3632 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 109786 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202470 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 315888 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16906807287 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16906807287 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 302000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 302000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 142927500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 142927500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 244477000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 244477000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7547443000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7547443000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244477000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7690370500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 7934847500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244477000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7690370500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16906807287 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 24841654787 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001913 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001913 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000703 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053249 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053249 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014308 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.039851 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7205861 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 801429 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 6779490 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 246291 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170011 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035851 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508607 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626218 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 23134825 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330879552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475136 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 554354688 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 545836 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 16398212 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.033285 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.179381 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 15852393 96.67% 96.67% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 545819 3.33% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 16398212 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 8661298500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 7755038952 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4135066975 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 314432 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66327 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 232586 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 18 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 18 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1379 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1379 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 314432 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 930571 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 930571 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24456832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 24456832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 614742 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 614742 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 614742 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 978145707 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1654146686 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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