250 lines
28 KiB
Text
250 lines
28 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 10400 # Simulator instruction rate (inst/s)
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host_mem_usage 205896 # Number of bytes of host memory used
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host_seconds 0.56 # Real time elapsed on the host
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host_tick_rate 53415864 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5827 # Number of instructions simulated
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sim_seconds 0.000030 # Number of seconds simulated
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sim_ticks 29940500 # Number of ticks simulated
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system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource.
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system.cpu.Branch-Predictor.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
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system.cpu.Branch-Predictor.predictedNotTaken 826 # Number of Branches Predicted As Not Taken (False).
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system.cpu.Branch-Predictor.predictedTaken 90 # Number of Branches Predicted As Taken (True).
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system.cpu.Decode-Unit.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
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system.cpu.Execution-Unit.instReqsProcessed 3734 # Number of Instructions Requests that completed in this resource.
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system.cpu.Execution-Unit.predictedNotTakenIncorrect 541 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.Execution-Unit.predictedTakenIncorrect 35 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.Fetch-Buffer-T0.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
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system.cpu.Fetch-Buffer-T0.instsBypassed 0 # Number of Instructions Bypassed.
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system.cpu.Fetch-Buffer-T1.instReqsProcessed 0 # Number of Instructions Requests that completed in this resource.
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system.cpu.Fetch-Buffer-T1.instsBypassed 0 # Number of Instructions Bypassed.
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system.cpu.Fetch-Seq-Unit.instReqsProcessed 11657 # Number of Instructions Requests that completed in this resource.
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system.cpu.Graduation-Unit.instReqsProcessed 5827 # Number of Instructions Requests that completed in this resource.
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system.cpu.Mult-Div-Unit.divInstReqsProcessed 1 # Number of Divide Requests Processed.
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system.cpu.Mult-Div-Unit.instReqsProcessed 8 # Number of Instructions Requests that completed in this resource.
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system.cpu.Mult-Div-Unit.multInstReqsProcessed 3 # Number of Multiply Requests Processed.
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system.cpu.RegFile-Manager.instReqsProcessed 10713 # Number of Instructions Requests that completed in this resource.
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system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
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system.cpu.cpi 10.276643 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi_total 10.276643 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1165 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56201.149425 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53201.149425 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1078 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4889500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.074678 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 4628500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.074678 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56554.687500 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.687500 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3619500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 3427500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 14.144928 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2090 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56350.993377 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1939 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 8509000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.072249 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.072249 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2090 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56350.993377 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53350.993377 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1939 # number of overall hits
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system.cpu.dcache.overall_miss_latency 8509000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.072249 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 151 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.072249 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 88.212490 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1952 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dcache_port.instReqsProcessed 2089 # Number of Instructions Requests that completed in this resource.
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55765.676568 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52765.676568 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 16897000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 15988000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55765.676568 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency
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system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 16897000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
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system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 15988000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55765.676568 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52765.676568 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 5526 # number of overall hits
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system.cpu.icache.overall_miss_latency 16897000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
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system.cpu.icache.overall_misses 303 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 15988000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 13 # number of replacements
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system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 134.267603 # Cycle average of tags in use
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system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache_port.instReqsProcessed 5828 # Number of Instructions Requests that completed in this resource.
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system.cpu.ipc 0.097308 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.ipc_total 0.097308 # IPC: Total IPC of All Threads
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52500 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 2677500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52052.835052 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40023.195876 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 20196500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 15529000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52538.461538 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40076.923077 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 683000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 521000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52104.783599 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 22874000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 17574000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52104.783599 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40031.890661 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 2 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 22874000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 439 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 17574000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 185.807591 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.numCycles 59882 # number of cpu cycles simulated
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was simultaneous multithreading.(SMT)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.threadCycles 59882 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
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---------- End Simulation Statistics ----------
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