d3d159749a
The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time.
205 lines
6.9 KiB
C++
205 lines
6.9 KiB
C++
/*
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* Copyright (c) 2013-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2012 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_DECODER_HH__
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#define __ARCH_ARM_DECODER_HH__
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#include <cassert>
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/types.hh"
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#include "arch/generic/decode_cache.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "enums/DecoderFlavour.hh"
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namespace ArmISA
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{
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class ISA;
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class Decoder
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{
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protected:
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//The extended machine instruction being generated
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ExtMachInst emi;
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MachInst data;
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bool bigThumb;
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bool instDone;
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bool outOfBytes;
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int offset;
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bool foundIt;
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ITSTATE itBits;
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int fpscrLen;
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int fpscrStride;
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Enums::DecoderFlavour decoderFlavour;
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/// A cache of decoded instruction objects.
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static GenericISA::BasicDecodeCache defaultCache;
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/**
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* Pre-decode an instruction from the current state of the
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* decoder.
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*/
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void process();
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/**
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* Consume bytes by moving the offset into the data word and
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* sanity check the results.
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*/
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void consumeBytes(int numBytes);
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public: // Decoder API
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Decoder(ISA* isa = nullptr);
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/** Reset the decoders internal state. */
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void reset();
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/**
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* Can the decoder accept more data?
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*
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* A CPU model uses this method to determine if the decoder can
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* accept more data. Note that an instruction can be ready (see
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* instReady() even if this method returns true.
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*/
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bool needMoreBytes() const { return outOfBytes; }
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/**
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* Is an instruction ready to be decoded?
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*
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* CPU models call this method to determine if decode() will
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* return a new instruction on the next call. It typically only
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* returns false if the decoder hasn't received enough data to
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* decode a full instruction.
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*/
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bool instReady() const { return instDone; }
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/**
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* Feed data to the decoder.
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*
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* A CPU model uses this interface to load instruction data into
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* the decoder. Once enough data has been loaded (check with
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* instReady()), a decoded instruction can be retrieved using
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* decode(ArmISA::PCState).
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*
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* This method is intended to support both fixed-length and
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* variable-length instructions. Instruction data is fetch in
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* MachInst blocks (which correspond to the size of a typical
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* insturction). The method might need to be called multiple times
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* if the instruction spans multiple blocks, in that case
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* needMoreBytes() will return true and instReady() will return
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* false.
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*
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* The fetchPC parameter is used to indicate where in memory the
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* instruction was fetched from. This is should be the same
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* address as the pc. If fetching multiple blocks, it indicates
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* where subsequent blocks are fetched from (pc + n *
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* sizeof(MachInst)).
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*
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* @param pc Instruction pointer that we are decoding.
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* @param fetchPC The address this chunk was fetched from.
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* @param inst Raw instruction data.
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*/
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void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
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/**
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* Decode an instruction or fetch it from the code cache.
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*
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* This method decodes the currently pending pre-decoded
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* instruction. Data must be fed to the decoder using moreBytes()
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* until instReady() is true before calling this method.
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*
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* @param pc Instruction pointer that we are decoding.
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* @return A pointer to a static instruction or NULL if the
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* decoder isn't ready (see instReady()).
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*/
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StaticInstPtr decode(ArmISA::PCState &pc);
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/**
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* Decode a pre-decoded machine instruction.
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*
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* @warn This method takes a pre-decoded instruction as its
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* argument. It should typically not be called directly.
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*
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* @param mach_inst A pre-decoded instruction
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* @retval A pointer to the corresponding StaticInst object.
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*/
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StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
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{
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return defaultCache.decode(this, mach_inst, addr);
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}
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/**
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* Decode a machine instruction without calling the cache.
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*
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* @note The implementation of this method is generated by the ISA
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* parser script.
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*
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* @warn This method takes a pre-decoded instruction as its
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* argument. It should typically not be called directly.
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*
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* @param mach_inst The binary instruction to decode.
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* @retval A pointer to the corresponding StaticInst object.
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*/
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StaticInstPtr decodeInst(ExtMachInst mach_inst);
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/**
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* Take over the state from an old decoder when switching CPUs.
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*
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* @param old Decoder used in old CPU
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*/
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void takeOverFrom(Decoder *old) {}
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public: // ARM-specific decoder state manipulation
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void setContext(FPSCR fpscr)
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{
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fpscrLen = fpscr.len;
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fpscrStride = fpscr.stride;
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}
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};
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} // namespace ArmISA
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#endif // __ARCH_ARM_DECODER_HH__
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