223 lines
7.3 KiB
Python
223 lines
7.3 KiB
Python
# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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intCodeTemplate = '''
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def rom
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{
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# This vectors the CPU into an interrupt handler in long mode.
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# On entry, t1 is set to the vector of the interrupt and t7 is the current
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# ip. We need that because rdip returns the next ip.
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extern %(startLabel)s:
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#
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# Get the 64 bit interrupt or trap gate descriptor from the IDT
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#
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# Load the gate descriptor from the IDT
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slli t4, t1, 4, dataSize=8
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ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8, atCPL0=True
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ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
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# Make sure the descriptor is a legal gate.
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chks t1, t4, %(gateCheckType)s
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#
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# Get the target CS descriptor using the selector in the gate
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# descriptor.
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#
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srli t10, t4, 16, dataSize=8
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andi t5, t10, 0xF8, dataSize=8
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andi t0, t10, 0x4, flags=(EZF,), dataSize=2
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br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,)
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ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
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br rom_local_label("%(startLabel)s_processDescriptor")
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%(startLabel)s_globalDescriptor:
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ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
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%(startLabel)s_processDescriptor:
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chks t10, t3, IntCSCheck, dataSize=8
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wrdl hs, t3, t10, dataSize=8
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# Stick the target offset in t9.
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wrdh t9, t4, t2, dataSize=8
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#
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# Figure out where the stack should be
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#
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# Record what we might set the stack selector to.
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rdsel t11, ss
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# Check if we're changing privelege level. At this point we can assume
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# we're going to a DPL that's less than or equal to the CPL.
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rdattr t10, hs, dataSize=8
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srli t10, t10, 3, dataSize=8
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andi t10, t10, 3, dataSize=8
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rdattr t5, cs, dataSize=8
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srli t5, t5, 3, dataSize=8
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andi t5, t5, 0x3, dataSize=8
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sub t0, t5, t10, flags=(EZF,), dataSize=8
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# We're going to change priviledge, so zero out the stack selector. We
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# need to let the IST have priority so we don't branch yet.
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wrsel t11, t0, flags=(nCEZF,)
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# Check the IST field of the gate descriptor
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srli t12, t4, 32, dataSize=8
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andi t12, t12, 0x7, dataSize=8
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subi t0, t12, 1, flags=(ECF,), dataSize=8
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br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,)
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br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,)
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# If we're here, it's because the stack isn't being switched.
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# Set t6 to the new aligned rsp.
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mov t6, t6, rsp, dataSize=8
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br rom_local_label("%(startLabel)s_stackSwitched")
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%(startLabel)s_istStackSwitch:
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ld t6, tr, [8, t12, t0], 0x1c, dataSize=8, addressSize=8, atCPL0=True
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br rom_local_label("%(startLabel)s_stackSwitched")
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%(startLabel)s_cplStackSwitch:
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# Get the new rsp from the TSS
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ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8, atCPL0=True
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%(startLabel)s_stackSwitched:
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andi t6, t6, 0xF0, dataSize=1
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subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
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##
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## Point of no return.
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## We're now going to irrevocably modify visible state.
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## Anything bad that's going to happen should have happened by now or will
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## happen right now.
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##
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wrip t0, t9, dataSize=8
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#
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# Set up the target code segment. Do this now so we have the right
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# permissions when setting up the stack frame.
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#
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srli t5, t4, 16, dataSize=8
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andi t5, t5, 0xFF, dataSize=8
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wrdl cs, t3, t5, dataSize=8
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# Tuck away the old CS for use below
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limm t10, 0, dataSize=8
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rdsel t10, cs, dataSize=2
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wrsel cs, t5, dataSize=2
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# Check that we can access everything we need to on the stack
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ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
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ldst t0, hs, [1, t0, t6], \
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32 + %(errorCodeSize)d, dataSize=8, addressSize=8
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#
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# Build up the interrupt stack frame
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#
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# Write out the contents of memory
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%(errorCodeCode)s
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st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8
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st t10, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8
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rflags t10, dataSize=8
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st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8
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st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8
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rdsel t5, ss, dataSize=2
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st t5, hs, [1, t0, t6], 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
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# Set the stack segment
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mov rsp, rsp, t6, dataSize=8
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wrsel ss, t11, dataSize=2
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#
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# Adjust rflags which is still in t10 from above
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#
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# Set IF to the lowest bit of the original gate type.
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# The type field of the original gate starts at bit 40.
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# Set the TF, NT, and RF bits. We'll flip them at the end.
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limm t6, (1 << 8) | (1 << 14) | (1 << 16)
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or t10, t10, t6
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srli t5, t4, 40, dataSize=8
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srli t7, t10, 9, dataSize=8
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xor t5, t7, t5, dataSize=8
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andi t5, t5, 1, dataSize=8
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slli t5, t5, 9, dataSize=8
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or t6, t5, t6, dataSize=8
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# Put the results into rflags
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wrflags t6, t10
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eret
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};
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'''
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microcode = \
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intCodeTemplate % {\
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"startLabel" : "longModeInterrupt",
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"gateCheckType" : "IntGateCheck",
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"errorCodeSize" : 0,
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"errorCodeCode" : ""
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} + \
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intCodeTemplate % {\
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"startLabel" : "longModeSoftInterrupt",
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"gateCheckType" : "SoftIntGateCheck",
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"errorCodeSize" : 0,
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"errorCodeCode" : ""
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} + \
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intCodeTemplate % {\
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"startLabel" : "longModeInterruptWithError",
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"gateCheckType" : "IntGateCheck",
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"errorCodeSize" : 8,
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"errorCodeCode" : '''
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st t15, hs, [1, t0, t6], dataSize=8, addressSize=8
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'''
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} + \
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'''
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def rom
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{
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# This vectors the CPU into an interrupt handler in legacy mode.
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extern legacyModeInterrupt:
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panic "Legacy mode interrupts not implemented (in microcode)"
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eret
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};
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def rom
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{
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extern initIntHalt:
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rflags t1
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limm t2, "~IFBit"
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and t1, t1, t2
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wrflags t1, t0
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halt
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eret
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};
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'''
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