eab89a09d2
--HG-- rename : util/statetrace/arch/tracechild_amd64.cc => util/statetrace/arch/amd64/tracechild.cc rename : util/statetrace/arch/tracechild_amd64.hh => util/statetrace/arch/amd64/tracechild.hh rename : util/statetrace/arch/tracechild_arm.cc => util/statetrace/arch/arm/tracechild.cc rename : util/statetrace/arch/tracechild_arm.hh => util/statetrace/arch/arm/tracechild.hh rename : util/statetrace/arch/tracechild_i386.cc => util/statetrace/arch/i386/tracechild.cc rename : util/statetrace/arch/tracechild_i386.hh => util/statetrace/arch/i386/tracechild.hh rename : util/statetrace/arch/tracechild_sparc.cc => util/statetrace/arch/sparc/tracechild.cc rename : util/statetrace/arch/tracechild_sparc.hh => util/statetrace/arch/sparc/tracechild.hh rename : util/statetrace/tracechild_arch.cc => util/statetrace/base/arch_check.h rename : util/statetrace/regstate.hh => util/statetrace/base/regstate.hh rename : util/statetrace/statetrace.cc => util/statetrace/base/statetrace.cc rename : util/statetrace/tracechild.cc => util/statetrace/base/tracechild.cc rename : util/statetrace/tracechild.hh => util/statetrace/base/tracechild.hh
404 lines
14 KiB
C++
404 lines
14 KiB
C++
/*
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* Copyright (c) 2007 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include <iostream>
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#include <iomanip>
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#include <errno.h>
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#include <sys/ptrace.h>
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#include <stdint.h>
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#include <string.h>
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#include "arch/amd64/tracechild.hh"
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using namespace std;
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bool
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AMD64TraceChild::sendState(int socket)
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{
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uint64_t regVal64 = 0;
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uint32_t regVal32 = 0;
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for (int x = 0; x <= R15; x++) {
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regVal64 = getRegVal(x);
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if (write(socket, ®Val64, sizeof(regVal64)) == -1) {
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cerr << "Write failed! " << strerror(errno) << endl;
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tracing = false;
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return false;
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}
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}
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regVal64 = getRegVal(RIP);
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if (write(socket, ®Val64, sizeof(regVal64)) == -1) {
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cerr << "Write failed! " << strerror(errno) << endl;
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tracing = false;
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return false;
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}
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for (int x = MMX0_0; x <= MMX7_1; x++) {
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regVal32 = getRegVal(x);
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if (write(socket, ®Val32, sizeof(regVal32)) == -1) {
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cerr << "Write failed! " << strerror(errno) << endl;
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tracing = false;
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return false;
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}
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}
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for (int x = XMM0_0; x <= XMM15_3; x++) {
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regVal32 = getRegVal(x);
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if (write(socket, ®Val32, sizeof(regVal32)) == -1) {
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cerr << "Write failed! " << strerror(errno) << endl;
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tracing = false;
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return false;
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}
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}
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return true;
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}
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int64_t
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AMD64TraceChild::getRegs(user_regs_struct & myregs,
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user_fpregs_struct & myfpregs, int num)
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{
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assert(num < numregs && num >= 0);
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switch (num) {
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//GPRs
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case RAX: return myregs.rax;
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case RBX: return myregs.rbx;
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case RCX: return myregs.rcx;
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case RDX: return myregs.rdx;
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//Index registers
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case RSI: return myregs.rsi;
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case RDI: return myregs.rdi;
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//Base pointer and stack pointer
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case RBP: return myregs.rbp;
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case RSP: return myregs.rsp;
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//New 64 bit mode registers
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case R8: return myregs.r8;
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case R9: return myregs.r9;
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case R10: return myregs.r10;
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case R11: return myregs.r11;
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case R12: return myregs.r12;
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case R13: return myregs.r13;
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case R14: return myregs.r14;
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case R15: return myregs.r15;
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//Segmentation registers
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case CS: return myregs.cs;
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case DS: return myregs.ds;
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case ES: return myregs.es;
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case FS: return myregs.fs;
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case GS: return myregs.gs;
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case SS: return myregs.ss;
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case FS_BASE: return myregs.fs_base;
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case GS_BASE: return myregs.gs_base;
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//PC
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case RIP: return myregs.rip;
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//Flags
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case EFLAGS: return myregs.eflags;
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//MMX
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case MMX0_0: return myfpregs.st_space[0];
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case MMX0_1: return myfpregs.st_space[1];
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case MMX1_0: return myfpregs.st_space[2];
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case MMX1_1: return myfpregs.st_space[3];
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case MMX2_0: return myfpregs.st_space[4];
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case MMX2_1: return myfpregs.st_space[5];
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case MMX3_0: return myfpregs.st_space[6];
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case MMX3_1: return myfpregs.st_space[7];
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case MMX4_0: return myfpregs.st_space[8];
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case MMX4_1: return myfpregs.st_space[9];
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case MMX5_0: return myfpregs.st_space[10];
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case MMX5_1: return myfpregs.st_space[11];
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case MMX6_0: return myfpregs.st_space[12];
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case MMX6_1: return myfpregs.st_space[13];
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case MMX7_0: return myfpregs.st_space[14];
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case MMX7_1: return myfpregs.st_space[15];
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//XMM
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case XMM0_0: return myfpregs.xmm_space[0];
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case XMM0_1: return myfpregs.xmm_space[1];
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case XMM0_2: return myfpregs.xmm_space[2];
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case XMM0_3: return myfpregs.xmm_space[3];
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case XMM1_0: return myfpregs.xmm_space[4];
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case XMM1_1: return myfpregs.xmm_space[5];
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case XMM1_2: return myfpregs.xmm_space[6];
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case XMM1_3: return myfpregs.xmm_space[7];
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case XMM2_0: return myfpregs.xmm_space[8];
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case XMM2_1: return myfpregs.xmm_space[9];
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case XMM2_2: return myfpregs.xmm_space[10];
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case XMM2_3: return myfpregs.xmm_space[11];
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case XMM3_0: return myfpregs.xmm_space[12];
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case XMM3_1: return myfpregs.xmm_space[13];
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case XMM3_2: return myfpregs.xmm_space[14];
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case XMM3_3: return myfpregs.xmm_space[15];
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case XMM4_0: return myfpregs.xmm_space[16];
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case XMM4_1: return myfpregs.xmm_space[17];
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case XMM4_2: return myfpregs.xmm_space[18];
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case XMM4_3: return myfpregs.xmm_space[19];
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case XMM5_0: return myfpregs.xmm_space[20];
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case XMM5_1: return myfpregs.xmm_space[21];
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case XMM5_2: return myfpregs.xmm_space[22];
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case XMM5_3: return myfpregs.xmm_space[23];
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case XMM6_0: return myfpregs.xmm_space[24];
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case XMM6_1: return myfpregs.xmm_space[25];
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case XMM6_2: return myfpregs.xmm_space[26];
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case XMM6_3: return myfpregs.xmm_space[27];
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case XMM7_0: return myfpregs.xmm_space[28];
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case XMM7_1: return myfpregs.xmm_space[29];
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case XMM7_2: return myfpregs.xmm_space[30];
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case XMM7_3: return myfpregs.xmm_space[31];
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case XMM8_0: return myfpregs.xmm_space[32];
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case XMM8_1: return myfpregs.xmm_space[33];
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case XMM8_2: return myfpregs.xmm_space[34];
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case XMM8_3: return myfpregs.xmm_space[35];
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case XMM9_0: return myfpregs.xmm_space[36];
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case XMM9_1: return myfpregs.xmm_space[37];
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case XMM9_2: return myfpregs.xmm_space[38];
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case XMM9_3: return myfpregs.xmm_space[39];
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case XMM10_0: return myfpregs.xmm_space[40];
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case XMM10_1: return myfpregs.xmm_space[41];
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case XMM10_2: return myfpregs.xmm_space[42];
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case XMM10_3: return myfpregs.xmm_space[43];
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case XMM11_0: return myfpregs.xmm_space[44];
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case XMM11_1: return myfpregs.xmm_space[45];
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case XMM11_2: return myfpregs.xmm_space[46];
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case XMM11_3: return myfpregs.xmm_space[47];
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case XMM12_0: return myfpregs.xmm_space[48];
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case XMM12_1: return myfpregs.xmm_space[49];
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case XMM12_2: return myfpregs.xmm_space[50];
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case XMM12_3: return myfpregs.xmm_space[51];
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case XMM13_0: return myfpregs.xmm_space[52];
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case XMM13_1: return myfpregs.xmm_space[53];
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case XMM13_2: return myfpregs.xmm_space[54];
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case XMM13_3: return myfpregs.xmm_space[55];
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case XMM14_0: return myfpregs.xmm_space[56];
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case XMM14_1: return myfpregs.xmm_space[57];
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case XMM14_2: return myfpregs.xmm_space[58];
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case XMM14_3: return myfpregs.xmm_space[59];
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case XMM15_0: return myfpregs.xmm_space[60];
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case XMM15_1: return myfpregs.xmm_space[61];
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case XMM15_2: return myfpregs.xmm_space[62];
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case XMM15_3: return myfpregs.xmm_space[63];
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default:
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assert(0);
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return 0;
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}
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}
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bool
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AMD64TraceChild::update(int pid)
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{
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oldregs = regs;
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oldfpregs = fpregs;
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if (ptrace(PTRACE_GETREGS, pid, 0, ®s) != 0) {
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cerr << "update: " << strerror(errno) << endl;
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return false;
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}
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if (ptrace(PTRACE_GETFPREGS, pid, 0, &fpregs) != 0) {
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cerr << "update: " << strerror(errno) << endl;
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return false;
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}
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for (unsigned int x = 0; x < numregs; x++)
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regDiffSinceUpdate[x] = (getRegVal(x) != getOldRegVal(x));
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return true;
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}
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AMD64TraceChild::AMD64TraceChild()
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{
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for (unsigned int x = 0; x < numregs; x++)
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regDiffSinceUpdate[x] = false;
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}
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int64_t
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AMD64TraceChild::getRegVal(int num)
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{
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return getRegs(regs, fpregs, num);
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}
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int64_t
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AMD64TraceChild::getOldRegVal(int num)
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{
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return getRegs(oldregs, oldfpregs, num);
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}
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ostream &
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AMD64TraceChild::outputStartState(ostream & os)
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{
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uint64_t sp = getSP();
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uint64_t pc = getPC();
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uint64_t highestInfo = 0;
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char obuf[1024];
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sprintf(obuf, "Initial stack pointer = 0x%016lx\n", sp);
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os << obuf;
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sprintf(obuf, "Initial program counter = 0x%016lx\n", pc);
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os << obuf;
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//Output the argument count
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uint64_t cargc = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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sprintf(obuf, "0x%016lx: Argc = 0x%016lx\n", sp, cargc);
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os << obuf;
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sp += 8;
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//Output argv pointers
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int argCount = 0;
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uint64_t cargv;
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do {
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cargv = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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sprintf(obuf, "0x%016lx: argv[%d] = 0x%016lx\n",
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sp, argCount++, cargv);
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if (cargv)
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if (highestInfo < cargv)
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highestInfo = cargv;
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os << obuf;
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sp += 8;
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} while(cargv);
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//Output the envp pointers
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int envCount = 0;
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uint64_t cenvp;
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do {
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cenvp = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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sprintf(obuf, "0x%016lx: envp[%d] = 0x%016lx\n",
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sp, envCount++, cenvp);
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os << obuf;
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sp += 8;
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} while(cenvp);
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uint64_t auxType, auxVal;
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do {
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auxType = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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sp += 8;
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auxVal = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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sp += 8;
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sprintf(obuf, "0x%016lx: Auxiliary vector = {0x%016lx, 0x%016lx}\n",
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sp - 16, auxType, auxVal);
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os << obuf;
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} while(auxType != 0 || auxVal != 0);
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//Print out the argument strings, environment strings, and file name.
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string current;
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uint64_t buf;
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uint64_t currentStart = sp;
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bool clearedInitialPadding = false;
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do {
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buf = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
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char * cbuf = (char *)&buf;
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for (int x = 0; x < sizeof(uint64_t); x++) {
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if (cbuf[x])
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current += cbuf[x];
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else {
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sprintf(obuf, "0x%016lx: \"%s\"\n",
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currentStart, current.c_str());
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os << obuf;
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current = "";
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currentStart = sp + x + 1;
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}
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}
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sp += 8;
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clearedInitialPadding = clearedInitialPadding || buf != 0;
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} while (!clearedInitialPadding || buf != 0 || sp <= highestInfo);
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return os;
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}
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uint64_t
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AMD64TraceChild::findSyscall()
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{
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uint64_t rip = getPC();
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bool foundOpcode = false;
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bool twoByteOpcode = false;
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for (;;) {
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uint64_t buf = ptrace(PTRACE_PEEKDATA, pid, rip, 0);
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for (int i = 0; i < sizeof(uint64_t); i++) {
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unsigned char byte = buf & 0xFF;
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if (!foundOpcode) {
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if(!(byte == 0x66 || //operand override
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byte == 0x67 || //address override
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byte == 0x2E || //cs
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byte == 0x3E || //ds
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byte == 0x26 || //es
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byte == 0x64 || //fs
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byte == 0x65 || //gs
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byte == 0x36 || //ss
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byte == 0xF0 || //lock
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byte == 0xF2 || //repe
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byte == 0xF3 || //repne
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(byte >= 0x40 && byte <= 0x4F) // REX
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)) {
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foundOpcode = true;
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}
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}
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if (foundOpcode) {
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if (twoByteOpcode) {
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//SYSCALL or SYSENTER
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if (byte == 0x05 || byte == 0x34)
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return rip + 1;
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else
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return 0;
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}
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if (!twoByteOpcode) {
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if (byte == 0xCC) // INT3
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return rip + 1;
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else if (byte == 0xCD) // INT with byte immediate
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return rip + 2;
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else if (byte == 0x0F) // two byte opcode prefix
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twoByteOpcode = true;
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else
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return 0;
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}
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}
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buf >>= 8;
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rip++;
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}
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}
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}
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bool
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AMD64TraceChild::step()
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{
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uint64_t ripAfterSyscall = findSyscall();
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if (ripAfterSyscall) {
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//Get the original contents of memory
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uint64_t buf = ptrace(PTRACE_PEEKDATA, pid, ripAfterSyscall, 0);
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//Patch the first two bytes of the memory immediately after this with
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//jmp -2. Either single stepping will take over before this
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//instruction, leaving the rip where it should be, or it will take
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//over after this instruction, -still- leaving the rip where it should
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//be.
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uint64_t newBuf = (buf & ~0xFFFF) | 0xFEEB;
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//Write the patched memory to the processes address space
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ptrace(PTRACE_POKEDATA, pid, ripAfterSyscall, newBuf);
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//Step and hit it
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ptraceSingleStep();
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//Put things back to the way they started
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ptrace(PTRACE_POKEDATA, pid, ripAfterSyscall, buf);
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} else {
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//Get all the way past repe and repne string instructions in one shot.
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uint64_t newPC, origPC = getPC();
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do {
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ptraceSingleStep();
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newPC = getPC();
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} while(newPC == origPC);
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}
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}
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TraceChild * genTraceChild()
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{
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return new AMD64TraceChild;
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}
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