d70f01ba5c
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout:
tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini:
tests/quick/50.memtest/ref/alpha/linux/memtest/config.out:
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt:
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout:
Update refs
--HG--
extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
406 lines
43 KiB
Plaintext
406 lines
43 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 162 # Number of BTB hits
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global.BPredUnit.BTBLookups 671 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 427 # Number of conditional branches predicted
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global.BPredUnit.lookups 860 # Number of BP lookups
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global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target.
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host_inst_rate 32334 # Simulator instruction rate (inst/s)
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host_mem_usage 153596 # Number of bytes of host memory used
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host_seconds 0.07 # Real time elapsed on the host
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host_tick_rate 21839716 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2387 # Number of instructions simulated
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sim_seconds 0.000002 # Number of seconds simulated
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sim_ticks 1619000 # Number of ticks simulated
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system.cpu.commit.COM:branches 396 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 2977
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 2102 7060.80%
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1 212 712.13%
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2 297 997.65%
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3 114 382.94%
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4 83 278.80%
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5 58 194.83%
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6 30 100.77%
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7 22 73.90%
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8 59 198.19%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 2576 # Number of instructions committed
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system.cpu.commit.COM:loads 415 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 709 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 2387 # Number of Instructions Simulated
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system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
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system.cpu.cpi 678.257227 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 678.257227 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 687 # number of overall hits
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system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 144 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use
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system.cpu.dcache.total_refs 687 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 860 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 736 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 3239
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system.cpu.fetch.rateDist.min_value 0
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0 2309 7128.74%
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1 47 145.11%
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2 82 253.16%
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3 70 216.12%
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4 128 395.18%
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5 58 179.07%
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6 37 114.23%
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7 46 142.02%
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8 462 1426.37%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency
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system.cpu.icache.demand_hits 543 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses
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system.cpu.icache.demand_misses 193 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 543 # number of overall hits
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system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses
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system.cpu.icache.overall_misses 193 # number of overall misses
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system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use
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system.cpu.icache.total_refs 543 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.iew.EXEC:branches 535 # Number of branches executed
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system.cpu.iew.EXEC:nop 256 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate
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system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 339 # Number of stores executed
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu.iew.WB:consumers 1857 # num instructions consuming a value
|
|
system.cpu.iew.WB:count 3126 # cumulative count of insts written-back
|
|
system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.WB:producers 1462 # num instructions producing a value
|
|
system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle
|
|
system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit
|
|
system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.001474 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.001474 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
(null) 0 0.00% # Type of FU issued
|
|
IntAlu 2413 71.45% # Type of FU issued
|
|
IntMult 1 0.03% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 617 18.27% # Type of FU issued
|
|
MemWrite 346 10.25% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
IntAlu 1 2.70% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 14 37.84% # attempts to use FU when none available
|
|
MemWrite 22 59.46% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 3239
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 2006 6193.27%
|
|
1 362 1117.63%
|
|
2 258 796.54%
|
|
3 236 728.62%
|
|
4 193 595.86%
|
|
5 111 342.70%
|
|
6 53 163.63%
|
|
7 14 43.22%
|
|
8 6 18.52%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 271 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 3239 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|