23bbec6a34
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
78 lines
2.4 KiB
Text
78 lines
2.4 KiB
Text
////////////////////////////////////////////////////////////////////
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//
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// Mem instructions
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//
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output header {{
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/**
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* Base class for integer operations.
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*/
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class Mem : public MipsStaticInst
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{
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protected:
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/// Constructor
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Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return "Disassembly of integer instruction\n";
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}
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}};
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def template MemExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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//Attempt to execute the instruction
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try
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{
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%(op_decl)s;
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%(op_rd)s;
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ea_code
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%(code)s;
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}
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//If we have an exception for some reason,
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//deal with it
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catch(MipsException except)
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{
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//Deal with exception
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return No_Fault;
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}
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//Write the resulting state to the execution context
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%(op_wb)s;
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return No_Fault;
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}
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}};
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// Primary format for integer operate instructions:
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def format Memory(code, ea_code = {{ EA = Rb + disp; }},*opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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exec_output = MemExecute.subst(iop)
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exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
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}};
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def format Cas(code, *opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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exec_output = MemExecute.subst(iop)
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exec_output.replace('ea_code', 'EA = R1;');
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}};
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