1119 lines
129 KiB
Plaintext
1119 lines
129 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.533116 # Number of seconds simulated
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sim_ticks 2533115780500 # Number of ticks simulated
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final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 55678 # Simulator instruction rate (inst/s)
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host_op_rate 71642 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 2338649550 # Simulator tick rate (ticks/s)
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host_mem_usage 398880 # Number of bytes of host memory used
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host_seconds 1083.15 # Real time elapsed on the host
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sim_insts 60307726 # Number of instructions simulated
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sim_ops 77599286 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory
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system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15096806 # Total number of read requests seen
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system.physmem.writeReqs 813108 # Total number of write requests seen
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system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 966195584 # Total number of bytes read from memory
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system.physmem.bytesWritten 52038912 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2533114676500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 36 # Categorize read packet sizes
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system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 154562 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 754018 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 59090 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see
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system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests
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system.physmem.totBusLat 75482470000 # Total cycles spent in databus access
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system.physmem.totBankLat 16917518750 # Total cycles spent in bank access
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system.physmem.avgQLat 26047.39 # Average queueing delay per request
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system.physmem.avgBankLat 1120.63 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 32168.02 # Average memory access latency
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system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.14 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.19 # Average read queue length over time
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system.physmem.avgWrQLen 11.11 # Average write queue length over time
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system.physmem.readRowHits 15020181 # Number of row buffer hits during reads
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system.physmem.writeRowHits 793022 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
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system.physmem.avgGap 159216.11 # Average gap between requests
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system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.branchPred.lookups 14672817 # Number of BP lookups
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system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions.
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system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
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system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
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system.cpu.checker.dtb.read_hits 14987449 # DTB read hits
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system.cpu.checker.dtb.read_misses 7302 # DTB read misses
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system.cpu.checker.dtb.write_hits 11227758 # DTB write hits
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system.cpu.checker.dtb.write_misses 2189 # DTB write misses
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|
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
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|
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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|
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
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|
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
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|
system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
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|
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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|
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
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|
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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|
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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|
system.cpu.checker.dtb.read_accesses 14994751 # DTB read accesses
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|
system.cpu.checker.dtb.write_accesses 11229947 # DTB write accesses
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|
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.checker.dtb.hits 26215207 # DTB hits
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system.cpu.checker.dtb.misses 9491 # DTB misses
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system.cpu.checker.dtb.accesses 26224698 # DTB accesses
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system.cpu.checker.itb.inst_hits 61481725 # ITB inst hits
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system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
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system.cpu.checker.itb.read_hits 0 # DTB read hits
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system.cpu.checker.itb.read_misses 0 # DTB read misses
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system.cpu.checker.itb.write_hits 0 # DTB write hits
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system.cpu.checker.itb.write_misses 0 # DTB write misses
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|
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
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|
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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|
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
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|
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
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|
system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB
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|
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
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|
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.checker.itb.inst_accesses 61486196 # ITB inst accesses
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system.cpu.checker.itb.hits 61481725 # DTB hits
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system.cpu.checker.itb.misses 4471 # DTB misses
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system.cpu.checker.itb.accesses 61486196 # DTB accesses
|
|
system.cpu.checker.numCycles 77885092 # number of cpu cycles simulated
|
|
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 51400888 # DTB read hits
|
|
system.cpu.dtb.read_misses 64225 # DTB read misses
|
|
system.cpu.dtb.write_hits 11700104 # DTB write hits
|
|
system.cpu.dtb.write_misses 15848 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 51465113 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 11715952 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 63100992 # DTB hits
|
|
system.cpu.dtb.misses 80073 # DTB misses
|
|
system.cpu.dtb.accesses 63181065 # DTB accesses
|
|
system.cpu.itb.inst_hits 12331220 # ITB inst hits
|
|
system.cpu.itb.inst_misses 11422 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 4954 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 12342642 # ITB inst accesses
|
|
system.cpu.itb.hits 12331220 # DTB hits
|
|
system.cpu.itb.misses 11422 # DTB misses
|
|
system.cpu.itb.accesses 12342642 # DTB accesses
|
|
system.cpu.numCycles 471822965 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued
|
|
system.cpu.iq.rate 0.263501 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 221132 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 11557425 # Number of branches executed
|
|
system.cpu.iew.exec_stores 12211932 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.257596 # Inst execution rate
|
|
system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 47248258 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 60458107 # Number of instructions committed
|
|
system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27386657 # Number of memory references committed
|
|
system.cpu.commit.loads 15654563 # Number of loads committed
|
|
system.cpu.commit.membars 403601 # Number of memory barriers committed
|
|
system.cpu.commit.branches 9961339 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 68854898 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 991261 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 242323943 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 202004834 # The number of ROB writes
|
|
system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.committedInsts 60307726 # Number of Instructions Simulated
|
|
system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 550297303 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 88455601 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8347 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2910 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 831893 # number of misc regfile writes
|
|
system.cpu.icache.replacements 979954 # number of replacements
|
|
system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11267650 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1060047 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 64333 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 51339.387704 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1885585 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 129729 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 14.534799 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2523139741500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 36938.518996 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.781617 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 8154.357820 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6219.728923 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.124426 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.094906 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.783377 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52369 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10535 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 967038 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 387148 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1417090 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 607758 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 607758 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 112914 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 112914 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 52369 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 10535 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 967038 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1530004 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 52369 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 10535 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 967038 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1530004 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12333 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 10696 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 23072 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12333 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 156276 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12333 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 156276 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2953500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695709500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 628176999 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1326957999 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6755691500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6755691500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2953500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 695709500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7383868499 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8082649499 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2953500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 695709500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7383868499 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8082649499 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52410 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10537 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 979371 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 397844 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1440162 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 607758 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 607758 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246118 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 246118 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52410 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10537 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 979371 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 643962 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1686280 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52410 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10537 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 979371 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 643962 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1686280 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000782 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012593 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026885 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016020 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986500 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986500 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541220 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541220 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000782 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012593 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223460 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.092675 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000782 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012593 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223460 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.092675 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72036.585366 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56410.402984 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58730.085920 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 57513.782897 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50716.881625 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50716.881625 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51720.350527 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51720.350527 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 59090 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 59090 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12321 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10636 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 23000 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133204 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133204 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12321 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 156204 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12321 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 156204 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2441041 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541729027 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 493322234 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1037585553 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5095490217 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5095490217 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2441041 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541729027 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5588812451 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6133075770 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2441041 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541729027 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5588812451 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6133075770 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002521767 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007602597 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911564456 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911564456 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914086223 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919167053 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026734 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015970 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986500 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986500 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541220 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541220 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092632 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092632 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43967.943105 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46382.308575 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45112.415348 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38253.282311 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38253.282311 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 643450 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 21511687 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 643962 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 33.405212 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13758946 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 21018060 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3699405 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3699405 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3699405 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3699405 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9739284500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9739284500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 104713593229 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 607758 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|