1f539f13c3
This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
72 lines
3.3 KiB
Python
72 lines
3.3 KiB
Python
# Copyright (c) 2005-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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class Process(SimObject):
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type = 'Process'
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abstract = True
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cxx_header = "sim/process.hh"
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input = Param.String('cin', "filename for stdin")
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output = Param.String('cout', 'filename for stdout')
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errout = Param.String('cerr', 'filename for stderr')
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system = Param.System(Parent.any, "system process will run on")
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useArchPT = Param.Bool('false', 'maintain an in-memory version of the page\
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table in an architecture-specific format')
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kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in SE')
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max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
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@classmethod
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def export_methods(cls, code):
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code('bool map(Addr vaddr, Addr paddr, int size, bool cacheable=true);')
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class EmulatedDriver(SimObject):
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type = 'EmulatedDriver'
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cxx_header = "sim/emul_driver.hh"
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abstract = True
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filename = Param.String("device file name (under /dev)")
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class LiveProcess(Process):
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type = 'LiveProcess'
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cxx_header = "sim/process.hh"
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executable = Param.String('', "executable (overrides cmd[0] if set)")
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cmd = VectorParam.String("command line (executable plus arguments)")
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env = VectorParam.String([], "environment settings")
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cwd = Param.String('', "current working directory")
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uid = Param.Int(100, 'user id')
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euid = Param.Int(100, 'effective user id')
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gid = Param.Int(100, 'group id')
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egid = Param.Int(100, 'effective group id')
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pid = Param.Int(100, 'process id')
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ppid = Param.Int(99, 'parent process id')
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simpoint = Param.UInt64(0, 'simulation point at which to start simulation')
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drivers = VectorParam.EmulatedDriver([], 'Available emulated drivers')
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