ed38e3432c
The drain() call currently passes around a DrainManager pointer, which is now completely pointless since there is only ever one global DrainManager in the system. It also contains vestiges from the time when SimObjects had to keep track of their child objects that needed draining. This changeset moves all of the DrainState handling to the Drainable base class and changes the drain() and drainResume() calls to reflect this. Particularly, the drain() call has been updated to take no parameters (the DrainManager argument isn't needed) and return a DrainState instead of an unsigned integer (there is no point returning anything other than 0 or 1 any more). Drainable objects should return either DrainState::Draining (equivalent to returning 1 in the old system) if they need more time to drain or DrainState::Drained (equivalent to returning 0 in the old system) if they are already in a consistent state. Returning DrainState::Running is considered an error. Drain done signalling is now done through the signalDrainDone() method in the Drainable class instead of using the DrainManager directly. The new call checks if the state of the object is DrainState::Draining before notifying the drain manager. This means that it is safe to call signalDrainDone() without first checking if the simulator has requested draining. The intention here is to reduce the code needed to implement draining in simple objects.
561 lines
17 KiB
C++
561 lines
17 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Device model for Intel's 8254x line of gigabit ethernet controllers.
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*/
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#ifndef __DEV_I8254XGBE_HH__
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#define __DEV_I8254XGBE_HH__
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#include <deque>
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#include <string>
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#include "base/cp_annotate.hh"
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#include "base/inet.hh"
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#include "debug/EthernetDesc.hh"
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#include "debug/EthernetIntr.hh"
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#include "dev/etherdevice.hh"
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#include "dev/etherint.hh"
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#include "dev/etherpkt.hh"
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#include "dev/i8254xGBe_defs.hh"
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#include "dev/pcidev.hh"
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#include "dev/pktfifo.hh"
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#include "params/IGbE.hh"
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#include "sim/eventq.hh"
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class IGbEInt;
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class IGbE : public EtherDevice
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{
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private:
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IGbEInt *etherInt;
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CPA *cpa;
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// device registers
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iGbReg::Regs regs;
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// eeprom data, status and control bits
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int eeOpBits, eeAddrBits, eeDataBits;
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uint8_t eeOpcode, eeAddr;
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uint16_t flash[iGbReg::EEPROM_SIZE];
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// packet fifos
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PacketFifo rxFifo;
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PacketFifo txFifo;
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// Packet that we are currently putting into the txFifo
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EthPacketPtr txPacket;
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// Should to Rx/Tx State machine tick?
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bool rxTick;
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bool txTick;
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bool txFifoTick;
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bool rxDmaPacket;
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// Number of bytes copied from current RX packet
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unsigned pktOffset;
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// Delays in managaging descriptors
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Tick fetchDelay, wbDelay;
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Tick fetchCompDelay, wbCompDelay;
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Tick rxWriteDelay, txReadDelay;
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// Event and function to deal with RDTR timer expiring
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void rdtrProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RDTR timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
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EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
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// Event and function to deal with RADV timer expiring
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void radvProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RADV timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
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EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
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// Event and function to deal with TADV timer expiring
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void tadvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TADV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
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EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
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// Event and function to deal with TIDV timer expiring
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void tidvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TIDV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
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EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
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// Main event to tick the device
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void tick();
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//friend class EventWrapper<IGbE, &IGbE::tick>;
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EventWrapper<IGbE, &IGbE::tick> tickEvent;
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uint64_t macAddr;
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void rxStateMachine();
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void txStateMachine();
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void txWire();
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/** Write an interrupt into the interrupt pending register and check mask
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* and interrupt limit timer before sending interrupt to CPU
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* @param t the type of interrupt we are posting
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* @param now should we ignore the interrupt limiting timer
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*/
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void postInterrupt(iGbReg::IntTypes t, bool now = false);
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/** Check and see if changes to the mask register have caused an interrupt
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* to need to be sent or perhaps removed an interrupt cause.
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*/
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void chkInterrupt();
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/** Send an interrupt to the cpu
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*/
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void delayIntEvent();
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void cpuPostInt();
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// Event to moderate interrupts
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EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
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/** Clear the interupt line to the cpu
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*/
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void cpuClearInt();
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Tick intClock() { return SimClock::Int::ns * 1024; }
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/** This function is used to restart the clock so it can handle things like
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* draining and resume in one place. */
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void restartClock();
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/** Check if all the draining things that need to occur have occured and
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* handle the drain event if so.
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*/
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void checkDrain();
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void anBegin(std::string sm, std::string st, int flags = CPA::FL_NONE) {
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if (cpa)
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cpa->hwBegin((CPA::flags)flags, sys, macAddr, sm, st);
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}
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void anQ(std::string sm, std::string q) {
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if (cpa)
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cpa->hwQ(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anDq(std::string sm, std::string q) {
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if (cpa)
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cpa->hwDq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anPq(std::string sm, std::string q, int num = 1) {
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if (cpa)
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cpa->hwPq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
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}
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void anRq(std::string sm, std::string q, int num = 1) {
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if (cpa)
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cpa->hwRq(CPA::FL_NONE, sys, macAddr, sm, q, macAddr, NULL, num);
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}
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void anWe(std::string sm, std::string q) {
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if (cpa)
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cpa->hwWe(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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void anWf(std::string sm, std::string q) {
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if (cpa)
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cpa->hwWf(CPA::FL_NONE, sys, macAddr, sm, q, macAddr);
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}
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template<class T>
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class DescCache : public Serializable
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{
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protected:
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virtual Addr descBase() const = 0;
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virtual long descHead() const = 0;
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virtual long descTail() const = 0;
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virtual long descLen() const = 0;
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virtual void updateHead(long h) = 0;
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virtual void enableSm() = 0;
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virtual void actionAfterWb() {}
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virtual void fetchAfterWb() = 0;
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typedef std::deque<T *> CacheType;
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CacheType usedCache;
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CacheType unusedCache;
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T *fetchBuf;
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T *wbBuf;
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// Pointer to the device we cache for
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IGbE *igbe;
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// Name of this descriptor cache
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std::string _name;
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// How far we've cached
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int cachePnt;
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// The size of the descriptor cache
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int size;
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// How many descriptors we are currently fetching
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int curFetching;
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// How many descriptors we are currently writing back
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int wbOut;
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// if the we wrote back to the end of the descriptor ring and are going
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// to have to wrap and write more
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bool moreToWb;
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// What the alignment is of the next descriptor writeback
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Addr wbAlignment;
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/** The packet that is currently being dmad to memory if any */
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EthPacketPtr pktPtr;
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/** Shortcut for DMA address translation */
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Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
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public:
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/** Annotate sm*/
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std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
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annUsedDescQ, annUnusedCacheQ, annDescQ;
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DescCache(IGbE *i, const std::string n, int s);
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virtual ~DescCache();
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std::string name() { return _name; }
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/** If the address/len/head change when we've got descriptors that are
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* dirty that is very bad. This function checks that we don't and if we
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* do panics.
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*/
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void areaChanged();
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void writeback(Addr aMask);
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void writeback1();
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EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
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/** Fetch a chunk of descriptors into the descriptor cache.
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* Calls fetchComplete when the memory system returns the data
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*/
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void fetchDescriptors();
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void fetchDescriptors1();
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EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
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/** Called by event when dma to read descriptors is completed
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*/
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void fetchComplete();
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EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
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/** Called by event when dma to writeback descriptors is completed
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*/
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void wbComplete();
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EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
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/* Return the number of descriptors left in the ring, so the device has
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* a way to figure out if it needs to interrupt.
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*/
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unsigned
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descLeft() const
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{
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unsigned left = unusedCache.size();
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if (cachePnt > descTail())
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left += (descLen() - cachePnt + descTail());
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else
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left += (descTail() - cachePnt);
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return left;
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}
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/* Return the number of descriptors used and not written back.
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*/
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unsigned descUsed() const { return usedCache.size(); }
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/* Return the number of cache unused descriptors we have. */
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unsigned descUnused() const { return unusedCache.size(); }
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/* Get into a state where the descriptor address/head/etc colud be
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* changed */
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void reset();
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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virtual bool hasOutstandingEvents() {
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return wbEvent.scheduled() || fetchEvent.scheduled();
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}
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};
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class RxDescCache : public DescCache<iGbReg::RxDesc>
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{
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protected:
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virtual Addr descBase() const { return igbe->regs.rdba(); }
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virtual long descHead() const { return igbe->regs.rdh(); }
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virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
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virtual long descTail() const { return igbe->regs.rdt(); }
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virtual void updateHead(long h) { igbe->regs.rdh(h); }
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virtual void enableSm();
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virtual void fetchAfterWb() {
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if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
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fetchDescriptors();
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}
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bool pktDone;
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/** Variable to head with header/data completion events */
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int splitCount;
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/** Bytes of packet that have been copied, so we know when to
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set EOP */
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unsigned bytesCopied;
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public:
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RxDescCache(IGbE *i, std::string n, int s);
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/** Write the given packet into the buffer(s) pointed to by the
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* descriptor and update the book keeping. Should only be called when
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* there are no dma's pending.
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* @param packet ethernet packet to write
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* @param pkt_offset bytes already copied from the packet to memory
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* @return pkt_offset + number of bytes copied during this call
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*/
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int writePacket(EthPacketPtr packet, int pkt_offset);
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/** Called by event when dma to write packet is completed
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*/
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void pktComplete();
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/** Check if the dma on the packet has completed and RX state machine
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* can continue
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*/
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bool packetDone();
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EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
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// Event to handle issuing header and data write at the same time
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// and only callking pktComplete() when both are completed
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void pktSplitDone();
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EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
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EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
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virtual bool hasOutstandingEvents();
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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};
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friend class RxDescCache;
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RxDescCache rxDescCache;
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class TxDescCache : public DescCache<iGbReg::TxDesc>
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{
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protected:
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virtual Addr descBase() const { return igbe->regs.tdba(); }
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virtual long descHead() const { return igbe->regs.tdh(); }
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virtual long descTail() const { return igbe->regs.tdt(); }
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virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
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virtual void updateHead(long h) { igbe->regs.tdh(h); }
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virtual void enableSm();
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virtual void actionAfterWb();
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virtual void fetchAfterWb() {
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if (!igbe->txTick && igbe->drainState() == DrainState::Running)
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fetchDescriptors();
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}
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bool pktDone;
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bool isTcp;
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bool pktWaiting;
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bool pktMultiDesc;
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Addr completionAddress;
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bool completionEnabled;
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uint32_t descEnd;
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// tso variables
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bool useTso;
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Addr tsoHeaderLen;
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Addr tsoMss;
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Addr tsoTotalLen;
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Addr tsoUsedLen;
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Addr tsoPrevSeq;
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Addr tsoPktPayloadBytes;
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bool tsoLoadedHeader;
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bool tsoPktHasHeader;
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uint8_t tsoHeader[256];
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Addr tsoDescBytesUsed;
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Addr tsoCopyBytes;
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int tsoPkts;
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public:
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TxDescCache(IGbE *i, std::string n, int s);
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/** Tell the cache to DMA a packet from main memory into its buffer and
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* return the size the of the packet to reserve space in tx fifo.
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* @return size of the packet
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*/
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unsigned getPacketSize(EthPacketPtr p);
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void getPacketData(EthPacketPtr p);
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void processContextDesc();
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/** Return the number of dsecriptors in a cache block for threshold
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* operations.
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*/
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unsigned
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descInBlock(unsigned num_desc)
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{
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return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
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}
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/** Ask if the packet has been transfered so the state machine can give
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* it to the fifo.
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* @return packet available in descriptor cache
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*/
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bool packetAvailable();
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/** Ask if we are still waiting for the packet to be transfered.
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* @return packet still in transit.
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*/
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bool packetWaiting() { return pktWaiting; }
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/** Ask if this packet is composed of multiple descriptors
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* so even if we've got data, we need to wait for more before
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* we can send it out.
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* @return packet can't be sent out because it's a multi-descriptor
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* packet
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*/
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bool packetMultiDesc() { return pktMultiDesc;}
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/** Called by event when dma to write packet is completed
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*/
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void pktComplete();
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EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
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void headerComplete();
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EventWrapper<TxDescCache, &TxDescCache::headerComplete> headerEvent;
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void completionWriteback(Addr a, bool enabled) {
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DPRINTF(EthernetDesc,
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"Completion writeback Addr: %#x enabled: %d\n",
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a, enabled);
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completionAddress = a;
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completionEnabled = enabled;
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}
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virtual bool hasOutstandingEvents();
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void nullCallback() {
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DPRINTF(EthernetDesc, "Completion writeback complete\n");
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}
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EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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};
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friend class TxDescCache;
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TxDescCache txDescCache;
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public:
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typedef IGbEParams Params;
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const Params *
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params() const {
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return dynamic_cast<const Params *>(_params);
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}
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IGbE(const Params *params);
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~IGbE();
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virtual void init();
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virtual EtherInt *getEthPort(const std::string &if_name, int idx);
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Tick lastInterrupt;
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virtual Tick read(PacketPtr pkt);
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virtual Tick write(PacketPtr pkt);
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virtual Tick writeConfig(PacketPtr pkt);
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bool ethRxPkt(EthPacketPtr packet);
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void ethTxDone();
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void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
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void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
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DrainState drain() M5_ATTR_OVERRIDE;
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void drainResume() M5_ATTR_OVERRIDE;
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};
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class IGbEInt : public EtherInt
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{
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private:
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IGbE *dev;
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public:
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IGbEInt(const std::string &name, IGbE *d)
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: EtherInt(name), dev(d)
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{ }
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virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
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virtual void sendDone() { dev->ethTxDone(); }
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};
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#endif //__DEV_I8254XGBE_HH__
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