ce8939a97e
Timing generator for a pixel-based display. The timing generator is intended for display processors driving a standard rasterized display. The simplest possible display processor needs to derive from this class and override the nextPixel() method to feed the display with pixel data. Pixels are ordered relative to the top left corner of the display. Scan lines appear in the following order: * Vertical Sync (starting at line 0) * Vertical back porch * Visible lines * Vertical front porch Pixel order within a scan line: * Horizontal Sync * Horizontal Back Porch * Visible pixels * Horizontal Front Porch All events in the timing generator are automatically suspended on a drain() request and restarted on drainResume(). This is conceptually equivalent to clock gating when the pixel clock while the system is draining. By gating the pixel clock, we prevent display controllers from disturbing a memory system that is about to drain.
122 lines
3.8 KiB
Python
122 lines
3.8 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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# Gabe Black
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Import('*')
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SimObject('Device.py')
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Source('io_device.cc')
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Source('isa_fake.cc')
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DebugFlag('IsaFake')
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if env['TARGET_ISA'] == 'null':
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Return()
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SimObject('BadDevice.py')
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SimObject('CopyEngine.py')
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SimObject('DiskImage.py')
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SimObject('Ethernet.py')
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SimObject('I2C.py')
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SimObject('Ide.py')
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SimObject('Pci.py')
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SimObject('Platform.py')
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SimObject('SimpleDisk.py')
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SimObject('Terminal.py')
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SimObject('Uart.py')
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Source('baddev.cc')
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Source('copy_engine.cc')
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Source('disk_image.cc')
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Source('dma_device.cc')
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Source('etherbus.cc')
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Source('etherdevice.cc')
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Source('etherdump.cc')
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Source('etherint.cc')
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Source('etherlink.cc')
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Source('multi_packet.cc')
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Source('multi_iface.cc')
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Source('multi_etherlink.cc')
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Source('tcp_iface.cc')
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Source('etherpkt.cc')
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Source('ethertap.cc')
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Source('i2cbus.cc')
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Source('i8254xGBe.cc')
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Source('ide_ctrl.cc')
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Source('ide_disk.cc')
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Source('intel_8254_timer.cc')
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Source('mc146818.cc')
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Source('ns_gige.cc')
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Source('pciconfigall.cc')
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Source('pcidev.cc')
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Source('pixelpump.cc')
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Source('pktfifo.cc')
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Source('platform.cc')
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Source('ps2.cc')
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Source('simple_disk.cc')
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Source('sinic.cc')
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Source('terminal.cc')
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Source('uart.cc')
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Source('uart8250.cc')
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DebugFlag('DiskImageRead')
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DebugFlag('DiskImageWrite')
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DebugFlag('DMA')
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DebugFlag('DMACopyEngine')
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DebugFlag('Ethernet')
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DebugFlag('MultiEthernet')
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DebugFlag('MultiEthernetPkt')
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DebugFlag('EthernetCksum')
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DebugFlag('EthernetDMA')
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DebugFlag('EthernetData')
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DebugFlag('EthernetDesc')
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DebugFlag('EthernetEEPROM')
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DebugFlag('EthernetIntr')
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DebugFlag('EthernetPIO')
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DebugFlag('EthernetSM')
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DebugFlag('IdeCtrl')
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DebugFlag('IdeDisk')
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DebugFlag('Intel8254Timer')
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DebugFlag('MC146818')
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DebugFlag('PCIDEV')
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DebugFlag('PciConfigAll')
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DebugFlag('SimpleDisk')
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DebugFlag('SimpleDiskData')
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DebugFlag('Terminal')
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DebugFlag('TerminalVerbose')
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DebugFlag('Uart')
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CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
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CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
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'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
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'EthernetCksum', 'EthernetEEPROM' ])
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CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
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'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
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CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
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