571 lines
10 KiB
INI
571 lines
10 KiB
INI
[root]
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type=Root
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children=system
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eventq_index=0
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full_system=false
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sim_quantum=0
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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eventq_index=0
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init_param=0
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kernel=
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kernel_addr_check=true
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load_addr_mask=1099511627775
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load_offset=0
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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mmap_using_noreserve=false
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[1]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.cpu0]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu0.l1c.cpu_side
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[system.cpu0.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu0.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.port
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mem_side=system.toL2Bus.slave[0]
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[system.cpu0.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu1]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu1.l1c.cpu_side
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[system.cpu1.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu1.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.port
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mem_side=system.toL2Bus.slave[1]
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[system.cpu1.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu2]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu2.l1c.cpu_side
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[system.cpu2.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu2.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.port
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mem_side=system.toL2Bus.slave[2]
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[system.cpu2.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu3]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu3.l1c.cpu_side
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[system.cpu3.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu3.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu3.port
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mem_side=system.toL2Bus.slave[3]
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[system.cpu3.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu4]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu4.l1c.cpu_side
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[system.cpu4.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu4.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu4.port
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mem_side=system.toL2Bus.slave[4]
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[system.cpu4.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu5]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu5.l1c.cpu_side
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[system.cpu5.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu5.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu5.port
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mem_side=system.toL2Bus.slave[5]
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[system.cpu5.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu6]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu6.l1c.cpu_side
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[system.cpu6.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu6.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu6.port
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mem_side=system.toL2Bus.slave[6]
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[system.cpu6.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu7]
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type=MemTest
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children=l1c
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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interval=1
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max_loads=100000
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percent_functional=50
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percent_reads=65
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percent_uncacheable=10
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progress_check=5000000
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progress_interval=10000
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size=65536
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suppress_func_warnings=false
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system=system
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port=system.cpu7.l1c.cpu_side
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[system.cpu7.l1c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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sequential_access=false
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size=32768
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system=system
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tags=system.cpu7.l1c.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu7.port
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mem_side=system.toL2Bus.slave[7]
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[system.cpu7.l1c.tags]
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type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
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sequential_access=false
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size=32768
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
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domain_id=-1
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eventq_index=0
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init_perf_level=0
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voltage_domain=system.voltage_domain
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[system.dvfs_handler]
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type=DVFSHandler
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domains=
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enable=false
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eventq_index=0
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sys_clk_domain=system.clk_domain
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transition_latency=100000000
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[system.l2c]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.cpu_clk_domain
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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max_miss_count=0
|
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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sequential_access=false
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size=65536
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system=system
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tags=system.l2c.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.toL2Bus.master[0]
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mem_side=system.membus.slave[0]
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[system.l2c.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=20
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sequential_access=false
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size=65536
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[system.membus]
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type=CoherentXBar
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clk_domain=system.clk_domain
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eventq_index=0
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forward_latency=4
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frontend_latency=3
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response_latency=2
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snoop_filter=Null
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snoop_response_latency=4
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system=system
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use_default_range=false
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width=16
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master=system.physmem.port
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slave=system.l2c.mem_side system.system_port
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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eventq_index=0
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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port=system.membus.master[0]
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[system.toL2Bus]
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type=CoherentXBar
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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forward_latency=0
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frontend_latency=1
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response_latency=1
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snoop_filter=Null
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snoop_response_latency=1
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system=system
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use_default_range=false
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width=32
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master=system.l2c.cpu_side
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slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
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[system.voltage_domain]
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type=VoltageDomain
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eventq_index=0
|
|
voltage=1.000000
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