8a652f9871
Re-enabling implicit parenting (see previous patch) causes current Ruby config scripts to create some strange hierarchies and generate several warnings. This patch makes three general changes to address these issues. 1. The order of object creation in the ruby config files makes the L1 caches children of the sequencer rather than the controller; these config ciles are rewritten to assign the L1 caches to the controller first. 2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports causes the sequencers to be children of system.ruby, generating warnings because they are already parented to their respective controllers. Changing this attribute to _cpu_ruby_ports fixes this because the leading underscore means this is now treated as a plain Python attribute rather than a child assignment. As a result, the configuration hierarchy changes such that, e.g., system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer. 3. In the topology classes, the routers become children of some random internal link node rather than direct children of the topology. The topology classes are rewritten to assign the routers to the topology object first. |
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.. | ||
inorder-timing.py | ||
memtest-ruby.py | ||
memtest.py | ||
o3-timing-mp-ruby.py | ||
o3-timing-mp.py | ||
o3-timing-ruby.py | ||
o3-timing.py | ||
pc-simple-atomic.py | ||
pc-simple-timing.py | ||
realview-o3.py | ||
realview-simple-atomic.py | ||
realview-simple-timing.py | ||
rubytest-ruby.py | ||
simple-atomic-mp-ruby.py | ||
simple-atomic-mp.py | ||
simple-atomic.py | ||
simple-timing-mp-ruby.py | ||
simple-timing-mp.py | ||
simple-timing-ruby.py | ||
simple-timing.py | ||
t1000-simple-atomic.py | ||
tsunami-o3-dual.py | ||
tsunami-o3.py | ||
tsunami-simple-atomic-dual.py | ||
tsunami-simple-atomic.py | ||
tsunami-simple-timing-dual.py | ||
tsunami-simple-timing.py | ||
twosys-tsunami-simple-atomic.py |