73 lines
7.2 KiB
Text
73 lines
7.2 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000052 # Number of seconds simulated
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sim_ticks 52498 # Number of ticks simulated
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final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000 # Frequency of simulated ticks
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host_inst_rate 9649 # Simulator instruction rate (inst/s)
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host_op_rate 9649 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 196549 # Simulator tick rate (ticks/s)
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host_mem_usage 151788 # Number of bytes of host memory used
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host_seconds 0.27 # Real time elapsed on the host
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sim_insts 2577 # Number of instructions simulated
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sim_ops 2577 # Number of ops (including micro ops) simulated
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system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
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system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
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system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 415 # DTB read hits
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system.cpu.dtb.read_misses 4 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 419 # DTB read accesses
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system.cpu.dtb.write_hits 294 # DTB write hits
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system.cpu.dtb.write_misses 4 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 298 # DTB write accesses
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system.cpu.dtb.data_hits 709 # DTB hits
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system.cpu.dtb.data_misses 8 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 717 # DTB accesses
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system.cpu.itb.fetch_hits 2586 # ITB hits
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system.cpu.itb.fetch_misses 11 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2597 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
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system.cpu.numCycles 52498 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 2577 # Number of instructions committed
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system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
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system.cpu.num_func_calls 140 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
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system.cpu.num_int_insts 2375 # number of integer instructions
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system.cpu.num_fp_insts 6 # number of float instructions
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system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 717 # number of memory refs
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system.cpu.num_load_insts 419 # Number of load instructions
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system.cpu.num_store_insts 298 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 52498 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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---------- End Simulation Statistics ----------
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