d32ee94231
This patch removes per processor cycle count, histogram for filter stats, histogram for multicasts, histogram for prefetch wait, some function prototypes that do not have definitions.
664 lines
23 KiB
C++
664 lines
23 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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This file has been modified by Kevin Moore and Dan Nussbaum of the
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Scalable Systems Research Group at Sun Microsystems Laboratories
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(http://research.sun.com/scalable/) to support the Adaptive
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Transactional Memory Test Platform (ATMTP).
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Please send email to atmtp-interest@sun.com with feedback, questions, or
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to request future announcements about ATMTP.
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----------------------------------------------------------------------
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File modification date: 2008-02-23
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----------------------------------------------------------------------
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*/
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// Allows use of times() library call, which determines virtual runtime
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#include <sys/resource.h>
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#include <sys/times.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <algorithm>
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#include <fstream>
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#include "base/stl_helpers.hh"
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#include "base/str.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/protocol/RubyRequest.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/profiler/AddressProfiler.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/system/Sequencer.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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using m5::stl_helpers::operator<<;
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static double process_memory_total();
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static double process_memory_resident();
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Profiler::Profiler(const Params *p)
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: SimObject(p)
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{
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m_inst_profiler_ptr = NULL;
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m_address_profiler_ptr = NULL;
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m_real_time_start_time = time(NULL); // Not reset in clearStats()
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m_hot_lines = p->hot_lines;
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m_all_instructions = p->all_instructions;
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m_num_of_sequencers = p->num_of_sequencers;
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m_hot_lines = false;
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m_all_instructions = false;
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m_address_profiler_ptr = new AddressProfiler(m_num_of_sequencers);
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m_address_profiler_ptr->setHotLines(m_hot_lines);
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m_address_profiler_ptr->setAllInstructions(m_all_instructions);
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if (m_all_instructions) {
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m_inst_profiler_ptr = new AddressProfiler(m_num_of_sequencers);
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m_inst_profiler_ptr->setHotLines(m_hot_lines);
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m_inst_profiler_ptr->setAllInstructions(m_all_instructions);
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}
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p->ruby_system->registerProfiler(this);
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}
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Profiler::~Profiler()
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{
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}
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void
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Profiler::print(ostream& out) const
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{
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out << "[Profiler]";
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}
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void
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Profiler::printRequestProfile(ostream &out) const
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{
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out << "Request vs. RubySystem State Profile" << endl;
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out << "--------------------------------" << endl;
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out << endl;
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map<string, uint64_t> m_requestProfileMap;
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uint64_t m_requests = 0;
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for (uint32_t i = 0; i < MachineType_NUM; i++) {
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for (map<uint32_t, AbstractController*>::iterator it =
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g_abs_controls[i].begin();
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it != g_abs_controls[i].end(); ++it) {
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AbstractController *ctr = (*it).second;
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map<string, uint64_t> mp = ctr->getRequestProfileMap();
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for (map<string, uint64_t>::iterator jt = mp.begin();
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jt != mp.end(); ++jt) {
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map<string, uint64_t>::iterator kt =
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m_requestProfileMap.find((*jt).first);
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if (kt != m_requestProfileMap.end()) {
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(*kt).second += (*jt).second;
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} else {
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m_requestProfileMap[(*jt).first] = (*jt).second;
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}
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}
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m_requests += ctr->getRequestCount();
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}
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}
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map<string, uint64_t>::const_iterator i = m_requestProfileMap.begin();
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map<string, uint64_t>::const_iterator end = m_requestProfileMap.end();
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for (; i != end; ++i) {
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const string &key = i->first;
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uint64_t count = i->second;
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double percent = (100.0 * double(count)) / double(m_requests);
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vector<string> items;
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tokenize(items, key, ':');
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vector<string>::iterator j = items.begin();
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vector<string>::iterator end = items.end();
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for (; j != end; ++i)
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out << setw(10) << *j;
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out << setw(11) << count;
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out << setw(14) << percent << endl;
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}
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out << endl;
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}
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void
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Profiler::printDelayProfile(ostream &out) const
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{
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out << "Message Delayed Cycles" << endl;
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out << "----------------------" << endl;
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uint32_t numVNets = Network::getNumberOfVirtualNetworks();
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Histogram delayHistogram;
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std::vector<Histogram> delayVCHistogram(numVNets);
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for (uint32_t i = 0; i < MachineType_NUM; i++) {
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for (map<uint32_t, AbstractController*>::iterator it =
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g_abs_controls[i].begin();
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it != g_abs_controls[i].end(); ++it) {
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AbstractController *ctr = (*it).second;
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delayHistogram.add(ctr->getDelayHist());
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for (uint32_t i = 0; i < numVNets; i++) {
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delayVCHistogram[i].add(ctr->getDelayVCHist(i));
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}
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}
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}
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out << "Total_delay_cycles: " << delayHistogram << endl;
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for (int i = 0; i < numVNets; i++) {
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out << " virtual_network_" << i << "_delay_cycles: "
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<< delayVCHistogram[i] << endl;
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}
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}
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void
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Profiler::printOutstandingReqProfile(ostream &out) const
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{
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Histogram sequencerRequests;
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for (uint32_t i = 0; i < MachineType_NUM; i++) {
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for (map<uint32_t, AbstractController*>::iterator it =
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g_abs_controls[i].begin();
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it != g_abs_controls[i].end(); ++it) {
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AbstractController *ctr = (*it).second;
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Sequencer *seq = ctr->getSequencer();
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if (seq != NULL) {
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sequencerRequests.add(seq->getOutstandReqHist());
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}
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}
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}
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out << "sequencer_requests_outstanding: "
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<< sequencerRequests << endl;
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}
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void
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Profiler::printStats(ostream& out, bool short_stats)
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{
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out << endl;
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if (short_stats) {
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out << "SHORT ";
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}
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out << "Profiler Stats" << endl;
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out << "--------------" << endl;
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time_t real_time_current = time(NULL);
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double seconds = difftime(real_time_current, m_real_time_start_time);
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double minutes = seconds / 60.0;
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double hours = minutes / 60.0;
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double days = hours / 24.0;
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Cycles ruby_cycles = g_system_ptr->curCycle()-m_ruby_start;
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if (!short_stats) {
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out << "Elapsed_time_in_seconds: " << seconds << endl;
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out << "Elapsed_time_in_minutes: " << minutes << endl;
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out << "Elapsed_time_in_hours: " << hours << endl;
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out << "Elapsed_time_in_days: " << days << endl;
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out << endl;
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}
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// print the virtual runtimes as well
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struct tms vtime;
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times(&vtime);
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seconds = (vtime.tms_utime + vtime.tms_stime) / 100.0;
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minutes = seconds / 60.0;
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hours = minutes / 60.0;
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days = hours / 24.0;
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out << "Virtual_time_in_seconds: " << seconds << endl;
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out << "Virtual_time_in_minutes: " << minutes << endl;
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out << "Virtual_time_in_hours: " << hours << endl;
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out << "Virtual_time_in_days: " << days << endl;
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out << endl;
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out << "Ruby_current_time: " << g_system_ptr->curCycle() << endl;
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out << "Ruby_start_time: " << m_ruby_start << endl;
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out << "Ruby_cycles: " << ruby_cycles << endl;
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out << endl;
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if (!short_stats) {
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out << "mbytes_resident: " << process_memory_resident() << endl;
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out << "mbytes_total: " << process_memory_total() << endl;
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if (process_memory_total() > 0) {
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out << "resident_ratio: "
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<< process_memory_resident()/process_memory_total() << endl;
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}
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out << endl;
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}
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if (!short_stats) {
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out << "Busy Controller Counts:" << endl;
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for (uint32_t i = 0; i < MachineType_NUM; i++) {
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uint32_t size = MachineType_base_count((MachineType)i);
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for (uint32_t j = 0; j < size; j++) {
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MachineID machID;
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machID.type = (MachineType)i;
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machID.num = j;
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AbstractController *ctr =
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(*(g_abs_controls[i].find(j))).second;
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out << machID << ":" << ctr->getFullyBusyCycles() << " ";
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if ((j + 1) % 8 == 0) {
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out << endl;
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}
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}
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out << endl;
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}
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out << endl;
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out << "Busy Bank Count:" << m_busyBankCount << endl;
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out << endl;
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printOutstandingReqProfile(out);
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out << endl;
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}
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if (!short_stats) {
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out << "All Non-Zero Cycle Demand Cache Accesses" << endl;
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out << "----------------------------------------" << endl;
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out << "miss_latency: " << m_allMissLatencyHistogram << endl;
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for (int i = 0; i < m_missLatencyHistograms.size(); i++) {
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if (m_missLatencyHistograms[i].size() > 0) {
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out << "miss_latency_" << RubyRequestType(i) << ": "
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<< m_missLatencyHistograms[i] << endl;
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}
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}
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for (int i = 0; i < m_machLatencyHistograms.size(); i++) {
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if (m_machLatencyHistograms[i].size() > 0) {
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out << "miss_latency_" << GenericMachineType(i) << ": "
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<< m_machLatencyHistograms[i] << endl;
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}
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}
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out << "miss_latency_wCC_issue_to_initial_request: "
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<< m_wCCIssueToInitialRequestHistogram << endl;
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out << "miss_latency_wCC_initial_forward_request: "
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<< m_wCCInitialRequestToForwardRequestHistogram << endl;
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out << "miss_latency_wCC_forward_to_first_response: "
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<< m_wCCForwardRequestToFirstResponseHistogram << endl;
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out << "miss_latency_wCC_first_response_to_completion: "
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<< m_wCCFirstResponseToCompleteHistogram << endl;
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out << "imcomplete_wCC_Times: " << m_wCCIncompleteTimes << endl;
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out << "miss_latency_dir_issue_to_initial_request: "
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<< m_dirIssueToInitialRequestHistogram << endl;
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out << "miss_latency_dir_initial_forward_request: "
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<< m_dirInitialRequestToForwardRequestHistogram << endl;
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out << "miss_latency_dir_forward_to_first_response: "
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<< m_dirForwardRequestToFirstResponseHistogram << endl;
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out << "miss_latency_dir_first_response_to_completion: "
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<< m_dirFirstResponseToCompleteHistogram << endl;
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out << "imcomplete_dir_Times: " << m_dirIncompleteTimes << endl;
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for (int i = 0; i < m_missMachLatencyHistograms.size(); i++) {
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for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) {
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if (m_missMachLatencyHistograms[i][j].size() > 0) {
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out << "miss_latency_" << RubyRequestType(i)
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<< "_" << GenericMachineType(j) << ": "
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<< m_missMachLatencyHistograms[i][j] << endl;
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}
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}
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}
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out << endl;
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out << "All Non-Zero Cycle SW Prefetch Requests" << endl;
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out << "------------------------------------" << endl;
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out << "prefetch_latency: " << m_allSWPrefetchLatencyHistogram << endl;
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for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
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if (m_SWPrefetchLatencyHistograms[i].size() > 0) {
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out << "prefetch_latency_" << RubyRequestType(i) << ": "
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<< m_SWPrefetchLatencyHistograms[i] << endl;
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}
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}
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for (int i = 0; i < m_SWPrefetchMachLatencyHistograms.size(); i++) {
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if (m_SWPrefetchMachLatencyHistograms[i].size() > 0) {
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out << "prefetch_latency_" << GenericMachineType(i) << ": "
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<< m_SWPrefetchMachLatencyHistograms[i] << endl;
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}
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}
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out << "prefetch_latency_L2Miss:"
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<< m_SWPrefetchL2MissLatencyHistogram << endl;
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if (m_all_sharing_histogram.size() > 0) {
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out << "all_sharing: " << m_all_sharing_histogram << endl;
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out << "read_sharing: " << m_read_sharing_histogram << endl;
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out << "write_sharing: " << m_write_sharing_histogram << endl;
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out << "all_sharing_percent: ";
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m_all_sharing_histogram.printPercent(out);
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out << endl;
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out << "read_sharing_percent: ";
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m_read_sharing_histogram.printPercent(out);
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out << endl;
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out << "write_sharing_percent: ";
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m_write_sharing_histogram.printPercent(out);
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out << endl;
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int64 total_miss = m_cache_to_cache + m_memory_to_cache;
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out << "all_misses: " << total_miss << endl;
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out << "cache_to_cache_misses: " << m_cache_to_cache << endl;
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out << "memory_to_cache_misses: " << m_memory_to_cache << endl;
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out << "cache_to_cache_percent: "
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<< 100.0 * (double(m_cache_to_cache) / double(total_miss))
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<< endl;
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out << "memory_to_cache_percent: "
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<< 100.0 * (double(m_memory_to_cache) / double(total_miss))
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<< endl;
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out << endl;
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}
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printRequestProfile(out);
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if (!m_all_instructions) {
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m_address_profiler_ptr->printStats(out);
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}
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if (m_all_instructions) {
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m_inst_profiler_ptr->printStats(out);
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}
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out << endl;
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printDelayProfile(out);
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printResourceUsage(out);
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}
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}
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void
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Profiler::printResourceUsage(ostream& out) const
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{
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out << endl;
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out << "Resource Usage" << endl;
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out << "--------------" << endl;
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int64_t pagesize = getpagesize(); // page size in bytes
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out << "page_size: " << pagesize << endl;
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rusage usage;
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getrusage (RUSAGE_SELF, &usage);
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out << "user_time: " << usage.ru_utime.tv_sec << endl;
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out << "system_time: " << usage.ru_stime.tv_sec << endl;
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out << "page_reclaims: " << usage.ru_minflt << endl;
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out << "page_faults: " << usage.ru_majflt << endl;
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out << "swaps: " << usage.ru_nswap << endl;
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out << "block_inputs: " << usage.ru_inblock << endl;
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out << "block_outputs: " << usage.ru_oublock << endl;
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}
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void
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Profiler::clearStats()
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{
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m_ruby_start = g_system_ptr->curCycle();
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m_real_time_start_time = time(NULL);
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m_busyBankCount = 0;
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m_missLatencyHistograms.resize(RubyRequestType_NUM);
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for (int i = 0; i < m_missLatencyHistograms.size(); i++) {
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m_missLatencyHistograms[i].clear(200);
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}
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m_machLatencyHistograms.resize(GenericMachineType_NUM+1);
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for (int i = 0; i < m_machLatencyHistograms.size(); i++) {
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m_machLatencyHistograms[i].clear(200);
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}
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m_missMachLatencyHistograms.resize(RubyRequestType_NUM);
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for (int i = 0; i < m_missLatencyHistograms.size(); i++) {
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m_missMachLatencyHistograms[i].resize(GenericMachineType_NUM+1);
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for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) {
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m_missMachLatencyHistograms[i][j].clear(200);
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}
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}
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m_allMissLatencyHistogram.clear(200);
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m_wCCIssueToInitialRequestHistogram.clear(200);
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m_wCCInitialRequestToForwardRequestHistogram.clear(200);
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m_wCCForwardRequestToFirstResponseHistogram.clear(200);
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m_wCCFirstResponseToCompleteHistogram.clear(200);
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m_wCCIncompleteTimes = 0;
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m_dirIssueToInitialRequestHistogram.clear(200);
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m_dirInitialRequestToForwardRequestHistogram.clear(200);
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m_dirForwardRequestToFirstResponseHistogram.clear(200);
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m_dirFirstResponseToCompleteHistogram.clear(200);
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m_dirIncompleteTimes = 0;
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m_SWPrefetchLatencyHistograms.resize(RubyRequestType_NUM);
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for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
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m_SWPrefetchLatencyHistograms[i].clear(200);
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}
|
|
m_SWPrefetchMachLatencyHistograms.resize(GenericMachineType_NUM+1);
|
|
for (int i = 0; i < m_SWPrefetchMachLatencyHistograms.size(); i++) {
|
|
m_SWPrefetchMachLatencyHistograms[i].clear(200);
|
|
}
|
|
m_allSWPrefetchLatencyHistogram.clear(200);
|
|
|
|
m_read_sharing_histogram.clear();
|
|
m_write_sharing_histogram.clear();
|
|
m_all_sharing_histogram.clear();
|
|
m_cache_to_cache = 0;
|
|
m_memory_to_cache = 0;
|
|
|
|
// update the start time
|
|
m_ruby_start = g_system_ptr->curCycle();
|
|
}
|
|
|
|
void
|
|
Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id)
|
|
{
|
|
if (msg.getType() != RubyRequestType_IFETCH) {
|
|
// Note: The following line should be commented out if you
|
|
// want to use the special profiling that is part of the GS320
|
|
// protocol
|
|
|
|
// NOTE: Unless PROFILE_HOT_LINES is enabled, nothing will be
|
|
// profiled by the AddressProfiler
|
|
m_address_profiler_ptr->
|
|
addTraceSample(msg.getLineAddress(), msg.getProgramCounter(),
|
|
msg.getType(), msg.getAccessMode(), id, false);
|
|
}
|
|
}
|
|
|
|
void
|
|
Profiler::profileSharing(const Address& addr, AccessType type,
|
|
NodeID requestor, const Set& sharers,
|
|
const Set& owner)
|
|
{
|
|
Set set_contacted(owner);
|
|
if (type == AccessType_Write) {
|
|
set_contacted.addSet(sharers);
|
|
}
|
|
set_contacted.remove(requestor);
|
|
int number_contacted = set_contacted.count();
|
|
|
|
if (type == AccessType_Write) {
|
|
m_write_sharing_histogram.add(number_contacted);
|
|
} else {
|
|
m_read_sharing_histogram.add(number_contacted);
|
|
}
|
|
m_all_sharing_histogram.add(number_contacted);
|
|
|
|
if (number_contacted == 0) {
|
|
m_memory_to_cache++;
|
|
} else {
|
|
m_cache_to_cache++;
|
|
}
|
|
}
|
|
|
|
void
|
|
Profiler::bankBusy()
|
|
{
|
|
m_busyBankCount++;
|
|
}
|
|
|
|
// non-zero cycle demand request
|
|
void
|
|
Profiler::missLatency(Cycles cycles,
|
|
RubyRequestType type,
|
|
const GenericMachineType respondingMach)
|
|
{
|
|
m_allMissLatencyHistogram.add(cycles);
|
|
m_missLatencyHistograms[type].add(cycles);
|
|
m_machLatencyHistograms[respondingMach].add(cycles);
|
|
m_missMachLatencyHistograms[type][respondingMach].add(cycles);
|
|
}
|
|
|
|
void
|
|
Profiler::missLatencyWcc(Cycles issuedTime,
|
|
Cycles initialRequestTime,
|
|
Cycles forwardRequestTime,
|
|
Cycles firstResponseTime,
|
|
Cycles completionTime)
|
|
{
|
|
if ((issuedTime <= initialRequestTime) &&
|
|
(initialRequestTime <= forwardRequestTime) &&
|
|
(forwardRequestTime <= firstResponseTime) &&
|
|
(firstResponseTime <= completionTime)) {
|
|
m_wCCIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime);
|
|
|
|
m_wCCInitialRequestToForwardRequestHistogram.add(forwardRequestTime -
|
|
initialRequestTime);
|
|
|
|
m_wCCForwardRequestToFirstResponseHistogram.add(firstResponseTime -
|
|
forwardRequestTime);
|
|
|
|
m_wCCFirstResponseToCompleteHistogram.add(completionTime -
|
|
firstResponseTime);
|
|
} else {
|
|
m_wCCIncompleteTimes++;
|
|
}
|
|
}
|
|
|
|
void
|
|
Profiler::missLatencyDir(Cycles issuedTime,
|
|
Cycles initialRequestTime,
|
|
Cycles forwardRequestTime,
|
|
Cycles firstResponseTime,
|
|
Cycles completionTime)
|
|
{
|
|
if ((issuedTime <= initialRequestTime) &&
|
|
(initialRequestTime <= forwardRequestTime) &&
|
|
(forwardRequestTime <= firstResponseTime) &&
|
|
(firstResponseTime <= completionTime)) {
|
|
m_dirIssueToInitialRequestHistogram.add(initialRequestTime - issuedTime);
|
|
|
|
m_dirInitialRequestToForwardRequestHistogram.add(forwardRequestTime -
|
|
initialRequestTime);
|
|
|
|
m_dirForwardRequestToFirstResponseHistogram.add(firstResponseTime -
|
|
forwardRequestTime);
|
|
|
|
m_dirFirstResponseToCompleteHistogram.add(completionTime -
|
|
firstResponseTime);
|
|
} else {
|
|
m_dirIncompleteTimes++;
|
|
}
|
|
}
|
|
|
|
// non-zero cycle prefetch request
|
|
void
|
|
Profiler::swPrefetchLatency(Cycles cycles, RubyRequestType type,
|
|
const GenericMachineType respondingMach)
|
|
{
|
|
m_allSWPrefetchLatencyHistogram.add(cycles);
|
|
m_SWPrefetchLatencyHistograms[type].add(cycles);
|
|
m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles);
|
|
|
|
if (respondingMach == GenericMachineType_Directory ||
|
|
respondingMach == GenericMachineType_NUM) {
|
|
m_SWPrefetchL2MissLatencyHistogram.add(cycles);
|
|
}
|
|
}
|
|
|
|
// Helper function
|
|
static double
|
|
process_memory_total()
|
|
{
|
|
// 4kB page size, 1024*1024 bytes per MB,
|
|
const double MULTIPLIER = 4096.0 / (1024.0 * 1024.0);
|
|
ifstream proc_file;
|
|
proc_file.open("/proc/self/statm");
|
|
int total_size_in_pages = 0;
|
|
int res_size_in_pages = 0;
|
|
proc_file >> total_size_in_pages;
|
|
proc_file >> res_size_in_pages;
|
|
return double(total_size_in_pages) * MULTIPLIER; // size in megabytes
|
|
}
|
|
|
|
static double
|
|
process_memory_resident()
|
|
{
|
|
// 4kB page size, 1024*1024 bytes per MB,
|
|
const double MULTIPLIER = 4096.0 / (1024.0 * 1024.0);
|
|
ifstream proc_file;
|
|
proc_file.open("/proc/self/statm");
|
|
int total_size_in_pages = 0;
|
|
int res_size_in_pages = 0;
|
|
proc_file >> total_size_in_pages;
|
|
proc_file >> res_size_in_pages;
|
|
return double(res_size_in_pages) * MULTIPLIER; // size in megabytes
|
|
}
|
|
|
|
void
|
|
Profiler::rubyWatch(int id)
|
|
{
|
|
uint64 tr = 0;
|
|
Address watch_address = Address(tr);
|
|
|
|
DPRINTFN("%7s %3s RUBY WATCH %d\n", g_system_ptr->curCycle(), id,
|
|
watch_address);
|
|
|
|
// don't care about success or failure
|
|
m_watch_address_set.insert(watch_address);
|
|
}
|
|
|
|
bool
|
|
Profiler::watchAddress(Address addr)
|
|
{
|
|
return m_watch_address_set.count(addr) > 0;
|
|
}
|
|
|
|
Profiler *
|
|
RubyProfilerParams::create()
|
|
{
|
|
return new Profiler(this);
|
|
}
|