cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
564 lines
65 KiB
Plaintext
564 lines
65 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000023 # Number of seconds simulated
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sim_ticks 23146500 # Number of ticks simulated
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final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 95077 # Simulator instruction rate (inst/s)
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host_op_rate 95070 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 145124480 # Simulator tick rate (ticks/s)
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host_mem_usage 230244 # Number of bytes of host memory used
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host_seconds 0.16 # Real time elapsed on the host
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sim_insts 15162 # Number of instructions simulated
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sim_ops 15162 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27904 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19072 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19072 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 436 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27904 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 27904 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 23113000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 436 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2156250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests
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system.physmem.totBusLat 2180000 # Total cycles spent in databus access
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system.physmem.totBankLat 7727500 # Total cycles spent in bank access
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system.physmem.avgQLat 4945.53 # Average queueing delay per request
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system.physmem.avgBankLat 17723.62 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27669.15 # Average memory access latency
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system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 9.42 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.52 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 339 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 53011.47 # Average gap between requests
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system.cpu.branchPred.lookups 5146 # Number of BP lookups
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system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 2719 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 46294 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 25496 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 3844 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 1541 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 2303 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 1055 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 68.582490 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 11045 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
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system.cpu.activity 37.948762 # Percentage of cycles cpu is active
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system.cpu.comLoads 2225 # Number of Load instructions committed
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system.cpu.comStores 1448 # Number of Store instructions committed
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system.cpu.comBranches 3358 # Number of Branches instructions committed
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system.cpu.comNops 726 # Number of Nop instructions committed
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system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
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system.cpu.comInts 7166 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 15162 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
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system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use
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system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 3004 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 3004 # number of overall hits
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system.cpu.icache.overall_hits::total 3004 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
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system.cpu.icache.overall_misses::total 381 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 3385 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 3385 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 3385 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112555 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 437 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14678000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3230000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 17908000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4625000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4625000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 14678000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7855000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 22533000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 14678000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7855000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 22533000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49090.301003 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60943.396226 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 50875 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54411.764706 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54411.764706 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 51562.929062 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49090.301003 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56920.289855 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 51562.929062 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 99.212064 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.024222 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.024222 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 3187 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 480 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3686000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3686000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19969500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 19969500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 23655500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 23655500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 23655500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 23655500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63551.724138 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 63551.724138 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47321.090047 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 47321.090047 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 49282.291667 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49282.291667 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 49282.291667 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 760 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.352941 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3284500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3284500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4713000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4713000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7997500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 7997500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7997500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 7997500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61971.698113 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61971.698113 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55447.058824 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55447.058824 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|