cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
939 lines
105 KiB
Plaintext
939 lines
105 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000024 # Number of seconds simulated
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sim_ticks 24473000 # Number of ticks simulated
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final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 87264 # Simulator instruction rate (inst/s)
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host_op_rate 87257 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 167537445 # Simulator tick rate (ticks/s)
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host_mem_usage 226344 # Number of bytes of host memory used
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host_seconds 0.15 # Real time elapsed on the host
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sim_insts 12745 # Number of instructions simulated
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62080 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 970 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 970 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 62080 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 24326500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 970 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 22645500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests
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system.physmem.totBusLat 4850000 # Total cycles spent in databus access
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system.physmem.totBankLat 25973750 # Total cycles spent in bank access
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system.physmem.avgQLat 23345.88 # Average queueing delay per request
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system.physmem.avgBankLat 26777.06 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 55122.94 # Average memory access latency
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system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 19.82 # Data bus utilization in percentage
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system.physmem.avgRdQLen 2.18 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 450 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 25078.87 # Average gap between requests
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system.cpu.branchPred.lookups 6101 # Number of BP lookups
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system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 1023 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4461 # DTB read hits
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system.cpu.dtb.read_misses 100 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4561 # DTB read accesses
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system.cpu.dtb.write_hits 2022 # DTB write hits
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system.cpu.dtb.write_misses 83 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 2105 # DTB write accesses
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system.cpu.dtb.data_hits 6483 # DTB hits
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system.cpu.dtb.data_misses 183 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 6666 # DTB accesses
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system.cpu.itb.fetch_hits 4836 # ITB hits
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system.cpu.itb.fetch_misses 49 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 4885 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload0.num_syscalls 17 # Number of system calls
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system.cpu.workload1.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 48947 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 4956 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 4731 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 10607 # Type of FU issued
|
|
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 10268 # Type of FU issued
|
|
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued
|
|
system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued
|
|
system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type::total 20875 # Type of FU issued
|
|
system.cpu.iq.rate 0.426482 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 98 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 81 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 179 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1527 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1521 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 3048 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1066 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1051 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2117 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.401046 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 4725 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 4632 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 9357 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 126869 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 53172 # The number of ROB writes
|
|
system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
|
system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 24701 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 13755 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.icache.replacements::0 6 # number of replacements
|
|
system.cpu.icache.replacements::1 0 # number of replacements
|
|
system.cpu.icache.replacements::total 6 # number of replacements
|
|
system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 3780 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 3780 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1049 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 78577996 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 78577996 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 78577996 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 4829 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 4829 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 4829 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 4829 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 4829 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 4829 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217229 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.217229 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.217229 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.217229 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.217229 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.217229 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74907.527169 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 74907.527169 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 74907.527169 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 74907.527169 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 3158 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 47.848485 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 425 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 425 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 425 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 425 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 425 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 425 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 624 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48453998 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 48453998 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48453998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 48453998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48453998 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 48453998 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129219 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.129219 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.129219 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77650.637821 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77650.637821 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 622 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 824 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 622 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 348 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 970 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 622 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 970 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 47808000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18056500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 65864500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12124000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 12124000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 47808000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30180500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 77988500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 47808000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30180500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 77988500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 624 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 826 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 624 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 348 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 972 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 624 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 348 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 972 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997579 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76861.736334 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89388.613861 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79932.645631 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83041.095890 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83041.095890 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 80400.515464 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 80400.515464 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 622 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 824 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 622 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 970 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 202.984846 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 4338 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 12.465517 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4338 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4338 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4338 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4338 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 320 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1028 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1028 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1028 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1028 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 26222500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 26222500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 53389967 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 53389967 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 79612467 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 79612467 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 79612467 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 79612467 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3636 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3636 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5366 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5366 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5366 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5366 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088009 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.088009 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.191577 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.191577 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.191577 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.191577 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81945.312500 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75409.557910 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 348 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|