760 lines
55 KiB
C
760 lines
55 KiB
C
#define OPTION_130 0
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#define OPTION_119 1
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#define OPTION_108 2
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#define OPTION_104 3
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#define OPTION_92 4
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#define OPTION_75 5
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#define OPTION_74 6
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#define OPTION_69 7
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#define OPTION_65 8
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#define OPTION_50 9
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#define OPTION_40 10
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#define OPTION_32 11
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#define OPTION_25 12
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#define OPTION_135 13
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#define OPTION_110 14
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#define PIXEL_BIAS 0
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struct isc_data {
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unsigned char data[56];
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};
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typedef struct isc_data ISC;
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struct monitor_data {
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int option;
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int monitor_rows;
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int monitor_columns;
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int sold_freq;
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int refresh_rate;
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int v_scanlines;
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int v_front_porch;
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int v_sync;
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int v_back_porch;
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int d_pixels;
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int h_pixels;
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int h_front_porch;
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int h_sync;
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int h_back_porch;
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int cursor_x;
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int cursor_y;
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ISC isc_data;
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};
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static struct monitor_data crystal_table[] =
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{
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{
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/* 130.808 Mhz */
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OPTION_130, /* Option number 1 */
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1024, /* rows */
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1280, /* columns */
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130, /* 130.8 Mhz */
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72, /* refresh rate */
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1024, /* v scanlines */
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3, /* v front porch */
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3, /* v sync */
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33, /* v back porch */
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1280, /* display pixels */
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1280, /* h pixels */
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32, /* h front porch */
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160, /* h sync */
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224, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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1,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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0,0,0,0,0,1, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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1,1,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,0,1,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 119.84 Mhz */
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OPTION_119, /* Option number 2 */
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1024, /* rows */
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1280, /* columns */
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119, /* 119 Mhz */
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66, /* refresh rate */
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1024, /* v scanlines */
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3, /* v front porch */
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3, /* v sync */
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33, /* v back porch */
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1280, /* display pixels */
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1280, /* h pixels */
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32, /* h front porch */
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160, /* h sync */
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224, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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1,0,0,1,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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1,1,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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0,1,0,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 108.18 Mhz */
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OPTION_108,
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1024, /* rows */
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1280, /* columns */
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108, /* 108 Mhz */
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60, /* refresh rate */
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1024, /* v scanlines */
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3, /* v front porch */
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3, /* v sync */
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26, /* v back porch */
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1280, /* display pixels */
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1280, /* h pixels */
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44, /* h front porch */
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184, /* h sync */
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200, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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1,0,1,0,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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0,0,1,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,0,0,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 104.00 Mhz */
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OPTION_104,
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900, /* rows */
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1152, /* columns */
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104, /* 104 Mhz */
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72, /* refresh rate */
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900, /* v scanlines */
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6, /* v front porch */
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10, /* v sync */
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44, /* v back porch */
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1152, /* display pixels */
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1152, /* h pixels */
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64, /* h front porch */
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112, /* h sync */
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176, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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1,0,1,0,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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0,1,1,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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0,1,0,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 92.98 Mhz */
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OPTION_92,
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900, /* rows */
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1152, /* columns */
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92, /* 92.98 Mhz */
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66, /* refresh rate */
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900, /* v scanlines */
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2, /* v front porch */
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4, /* v sync */
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31, /* v back porch */
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1152, /* display pixels */
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1152, /* h pixels */
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20, /* h front porch */
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132, /* h sync */
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200, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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0,0,1,1,0,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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0,0,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,0,1,1,0,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 75.00 Mhz */
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OPTION_75,
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768, /* rows */
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1024, /* columns */
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75, /* 74 Mhz */
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70, /* refresh rate */
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768, /* v scanlines */
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3, /* v front porch */
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6, /* v sync */
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29, /* v back porch */
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1024, /* display pixels */
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1024, /* h pixels */
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24, /* h front porch */
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136, /* h sync */
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144, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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1,0,0,0,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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0,1,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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0,0,1,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 74.37 Mhz */
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OPTION_74,
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768, /* rows */
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1024, /* columns */
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74, /* 74 Mhz */
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72, /* refresh rate */
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768, /* v scanlines */
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1, /* v front porch */
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6, /* v sync */
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22, /* v back porch */
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1024, /* display pixels */
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1024, /* h pixels */
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16, /* h front porch */
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128, /* h sync */
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128, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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0,1,1,1,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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1,0,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,1,0,0,0,1,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 69 Mhz DEC 72 Hz */
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OPTION_69, /* Option number 3 */
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864, /* rows */
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1024+PIXEL_BIAS, /* columns */
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69, /* 69.x Mhz */
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60, /* refresh rate */
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864, /* v scanlines */
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0, /* v front porch */
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3, /* v sync */
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34, /* v back porch */
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1024, /* display pixels */
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1024+PIXEL_BIAS, /* h pixels */
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12, /* h front porch */
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116, /* h sync */
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128, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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{
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1,0,0, /* 0:1 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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1,0,1,1,0,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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1,1,0,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,0,0,0,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 65 Mhz */
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OPTION_65,
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768, /* rows */
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1024, /* columns */
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65, /* 65 Mhz */
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60, /* refresh rate */
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768, /* v scanlines */
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7, /* v front porch */
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9, /* v sync */
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26, /* v back porch */
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1024, /* display pixels */
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1024, /* h pixels */
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56, /* h front porch */
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64, /* h sync */
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200, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
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0, /* 6 toggle for ramdac reset */
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0, /* 7 1 to pass reference frequency */
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0, /* 8 1 for N1 and N2 dividers */
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0, /* 9 VRAM shift clock enable */
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0, /* 10 External PLL feedback */
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0, /* 11 phase detect reset */
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0,0, /* 12:13 PLL post scaler bits */
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0, /* 14 aux clock differential */
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0, /* 15 auxen clock mode */
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1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
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0,0,1, /* 24:26 sets the gain of VCO */
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0, /* 27 bit 28 for N2 */
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0,1, /* 28:29 sets gain of phase detector */
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0, /* 30 reserved */
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0, /* 31 phase detector timing */
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0,1,0,0,1,0, /* 32:37 M counter bits */
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0, /* 38 reserved */
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0, /* 39 doubles the modulus prescale */
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0,0,1,0, /* 40:43 A counter */
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0,0,0,0, /* 44:47 reserved */
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1,0,0,1,1,0,0, /* 48:54 Reference divider */
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0, /* 55 reserved */
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}
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},
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{ /* 50 Mhz ergo SVGA */
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OPTION_50,
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600, /* rows */
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800, /* columns */
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50, /* 50 Mhz */
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72, /* refresh rate */
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600, /* v scanlines */
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31, /* v front porch */
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6, /* v sync */
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29, /* v back porch */
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800 , /* display pixels */
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800, /* h pixels */
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56, /* h front porch */
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120, /* h sync */
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64, /* h back porch */
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0, /* cursor x placeholder */
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0, /* cursor y placeholder */
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/* ISC serial load information */
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{
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1,0,0, /* 0:2 N1 modulus */
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0,0, /* 3:4 set to zero */
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0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
0,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
0,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
1,0,0,0,1,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
1,0,0,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
0,1,1,1,1,0,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
},
|
||
{ /* 40 Mhz SVGA */
|
||
OPTION_40,
|
||
600, /* rows */
|
||
800, /* columns */
|
||
40, /* 36 Mhz */
|
||
60, /* refresh rate */
|
||
600, /* v scanlines */
|
||
1, /* v front porch */
|
||
4, /* v sync */
|
||
23, /* v back porch */
|
||
800, /* display pixels */
|
||
800, /* h pixels */
|
||
40, /* h front porch */
|
||
128, /* h sync */
|
||
88, /* h back porch */
|
||
0, /* cursor x placeholder */
|
||
0, /* cursor y placeholder */
|
||
/* ISC serial load information */
|
||
|
||
{
|
||
1,0,0, /* 0:2 N1 modulus */
|
||
0,0, /* 3:4 set to zero */
|
||
0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
0,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
0,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
0,1,1,1,0,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
1,0,1,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
1,0,0,0,0,1,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
},
|
||
{ /* 31.5 Mhz ergo VGA */
|
||
OPTION_32,
|
||
480, /* rows */
|
||
640, /* columns */
|
||
32, /* 32 Mhz */
|
||
72, /* refresh rate */
|
||
480, /* v scanlines */
|
||
9, /* v front porch */
|
||
3, /* v sync */
|
||
28, /* v back porch */
|
||
640, /* display pixels */
|
||
640, /* h pixels */
|
||
24, /* h front porch */
|
||
40, /* h sync */
|
||
128, /* h back porch */
|
||
0, /* cursor x placeholder */
|
||
0, /* cursor y placeholder */
|
||
|
||
/* ISC serial load information */
|
||
|
||
{
|
||
1,0,0, /* 0:2 N1 modulus */
|
||
0,0, /* 3:4 set to zero */
|
||
0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
1,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
0,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
1,0,1,1,0,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
0,0,1,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
1,1,0,0,1,0,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
},
|
||
{ /* 25.175 Mhz VGA */
|
||
OPTION_25, /* Option Information */
|
||
480, /* rows */
|
||
640, /* columns */
|
||
25, /* 25.175 Mhz */
|
||
60, /* refresh rate */
|
||
480, /* v scanlines */
|
||
10, /* v front porch */
|
||
2, /* v sync */
|
||
33, /* v back porch */
|
||
640, /* display pixels */
|
||
640, /* h pixels */
|
||
16, /* h front porch */
|
||
96, /* h sync */
|
||
48, /* h back porch */
|
||
0, /* cursor x placeholder */
|
||
0, /* cursor y placeholder */
|
||
/* ISC serial load information */
|
||
|
||
{
|
||
1,0,0, /* 0:2 N1 modulus */
|
||
0,0, /* 3:4 set to zero */
|
||
0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
1,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
0,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
1,0,0,0,1,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
1,0,0,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
0,1,1,1,1,0,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
},
|
||
{ /* 135 Mhz */
|
||
OPTION_135, /* Option number D */
|
||
1024, /* rows */
|
||
1280, /* columns */
|
||
135, /* 135 Mhz */
|
||
75, /* refresh rate */
|
||
1024, /* v scanlines */
|
||
1, /* v front porch */
|
||
3, /* v sync */
|
||
38, /* v back porch */
|
||
1280, /* display pixels */
|
||
1280, /* h pixels */
|
||
16, /* h front porch */
|
||
144, /* h sync */
|
||
248, /* h back porch */
|
||
0, /* cursor x placeholder */
|
||
0, /* cursor y placeholder */
|
||
|
||
/* ISC serial load information */
|
||
|
||
{
|
||
1,0,0, /* 0:2 N1 modulus */
|
||
0,0, /* 3:4 set to zero */
|
||
0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
0,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
1,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
0,0,1,0,1,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
0,1,1,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
1,0,1,1,0,0,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
},
|
||
{ /* 110 Mhz */
|
||
OPTION_110, /* Option number E */
|
||
1024, /* rows */
|
||
1280, /* columns */
|
||
110, /* 110 Mhz */
|
||
60, /* refresh rate */
|
||
1024, /* v scanlines */
|
||
6, /* v front porch */
|
||
7, /* v sync */
|
||
44, /* v back porch */
|
||
1280, /* display pixels */
|
||
1280, /* h pixels */
|
||
19, /* h front porch */
|
||
163, /* h sync */
|
||
234, /* h back porch */
|
||
0, /* cursor x placeholder */
|
||
0, /* cursor y placeholder */
|
||
|
||
/* ISC serial load information */
|
||
|
||
{
|
||
1,0,0, /* 0:2 N1 modulus */
|
||
0,0, /* 3:4 set to zero */
|
||
0, /* 5 tristates PLL */
|
||
0, /* 6 toggle for ramdac reset */
|
||
0, /* 7 1 to pass reference frequency */
|
||
0, /* 8 1 for N1 and N2 dividers */
|
||
0, /* 9 VRAM shift clock enable */
|
||
0, /* 10 External PLL feedback */
|
||
0, /* 11 phase detect reset */
|
||
0,0, /* 12:13 PLL post scaler bits */
|
||
0, /* 14 aux clock differential */
|
||
0, /* 15 auxen clock mode */
|
||
1,0,0,0,0,0,0,0, /* 16:23 N2 modulus */
|
||
0,0,1, /* 24:26 sets the gain of VCO */
|
||
0, /* 27 bit 28 for N2 */
|
||
0,1, /* 28:29 sets gain of phase detector */
|
||
0, /* 30 reserved */
|
||
0, /* 31 phase detector timing */
|
||
1,1,1,1,0,0, /* 32:37 M counter bits */
|
||
0, /* 38 reserved */
|
||
0, /* 39 doubles the modulus prescale */
|
||
0,0,1,0, /* 40:43 A counter */
|
||
0,0,0,0, /* 44:47 reserved */
|
||
0,0,1,1,0,0,0, /* 48:54 Reference divider */
|
||
0, /* 55 reserved */
|
||
}
|
||
}
|
||
};
|