d228db1143
The value in EAX has an 8 bit field for the linear address size and one for the physical address size when calling that function. A recent change implemented it but returned 0xff for both of those fields. That implies that linear and physical addresses are 255 bits wide which is wrong. When using the KVM CPU model this causes an error, presumably because some of those bits are actually reserved, or the CPU or kernel realizes 255 bits is a bad value. This change makes those values 48.
170 lines
6.5 KiB
C++
170 lines
6.5 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/cpuid.hh"
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#include "base/bitfield.hh"
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#include "cpu/thread_context.hh"
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namespace X86ISA {
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enum StandardCpuidFunction {
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VendorAndLargestStdFunc,
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FamilyModelStepping,
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NumStandardCpuidFuncs
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};
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enum ExtendedCpuidFunctions {
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VendorAndLargestExtFunc,
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FamilyModelSteppingBrandFeatures,
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NameString1,
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NameString2,
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NameString3,
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L1CacheAndTLB,
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L2L3CacheAndL2TLB,
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APMInfo,
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LongModeAddressSize,
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/*
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* The following are defined by the spec but not yet implemented
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*/
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/* // Function 9 is reserved
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SVMInfo = 10,
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// Functions 11-24 are reserved
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TLB1GBPageInfo = 25,
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PerformanceInfo,*/
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NumExtendedCpuidFuncs
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};
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static const int vendorStringSize = 13;
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static const char vendorString[vendorStringSize] = "M5 Simulator";
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static const int nameStringSize = 48;
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static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU";
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uint64_t
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stringToRegister(const char *str)
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{
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uint64_t reg = 0;
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for (int pos = 3; pos >=0; pos--) {
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reg <<= 8;
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reg |= str[pos];
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}
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return reg;
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}
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bool
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doCpuid(ThreadContext * tc, uint32_t function,
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uint32_t index, CpuidResult &result)
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{
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uint16_t family = bits(function, 31, 16);
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uint16_t funcNum = bits(function, 15, 0);
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if (family == 0x8000) {
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// The extended functions
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switch (funcNum) {
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case VendorAndLargestExtFunc:
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assert(vendorStringSize >= 12);
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result = CpuidResult(
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0x80000000 + NumExtendedCpuidFuncs - 1,
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stringToRegister(vendorString),
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stringToRegister(vendorString + 4),
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stringToRegister(vendorString + 8));
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break;
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case FamilyModelSteppingBrandFeatures:
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result = CpuidResult(0x00020f51, 0x00000405,
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0xe3d3fbff, 0x00000001);
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break;
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case NameString1:
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case NameString2:
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case NameString3:
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{
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// Zero fill anything beyond the end of the string. This
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// should go away once the string is a vetted parameter.
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char cleanName[nameStringSize];
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memset(cleanName, '\0', nameStringSize);
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strncpy(cleanName, nameString, nameStringSize);
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int offset = (funcNum - NameString1) * 16;
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assert(nameStringSize >= offset + 16);
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result = CpuidResult(
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stringToRegister(cleanName + offset + 0),
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stringToRegister(cleanName + offset + 4),
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stringToRegister(cleanName + offset + 12),
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stringToRegister(cleanName + offset + 8));
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}
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break;
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case L1CacheAndTLB:
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result = CpuidResult(0xff08ff08, 0xff20ff20,
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0x40020140, 0x40020140);
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break;
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case L2L3CacheAndL2TLB:
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result = CpuidResult(0x00000000, 0x42004200,
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0x00000000, 0x04008140);
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break;
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case APMInfo:
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result = CpuidResult(0x80000018, 0x68747541,
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0x69746e65, 0x444d4163);
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break;
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case LongModeAddressSize:
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result = CpuidResult(0x00003030, 0x00000000,
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0x00000000, 0x00000000);
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break;
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/* case SVMInfo:
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case TLB1GBPageInfo:
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case PerformanceInfo:*/
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default:
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warn("x86 cpuid: unimplemented function %u", funcNum);
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return false;
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}
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} else if(family == 0x0000) {
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// The standard functions
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switch (funcNum) {
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case VendorAndLargestStdFunc:
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assert(vendorStringSize >= 12);
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result = CpuidResult(
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NumStandardCpuidFuncs - 1,
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stringToRegister(vendorString),
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stringToRegister(vendorString + 4),
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stringToRegister(vendorString + 8));
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break;
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case FamilyModelStepping:
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result = CpuidResult(0x00020f51, 0x00000805,
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0xe7dbfbff, 0x00000001);
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break;
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default:
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warn("x86 cpuid: unimplemented function %u", funcNum);
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return false;
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}
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} else {
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warn("x86 cpuid: unknown family %#x", family);
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return false;
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}
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return true;
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}
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} // namespace X86ISA
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