247 lines
28 KiB
Text
247 lines
28 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1190065 # Simulator instruction rate (inst/s)
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host_mem_usage 201788 # Number of bytes of host memory used
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host_seconds 1251.63 # Real time elapsed on the host
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host_tick_rate 1654548560 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1489514860 # Number of instructions simulated
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sim_seconds 2.070875 # Number of seconds simulated
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sim_ticks 2070875212000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 23237.213149 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21237.213149 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4495936000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 4108976000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 1000000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 920000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 166527019 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 7990575000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001916 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 319623 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 7351329000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.001916 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 319623 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 1255.221220 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 24335.291355 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 568845227 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 12486511000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 513103 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 11460305000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 513103 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 24335.291355 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 22335.291355 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 568845227 # number of overall hits
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system.cpu.dcache.overall_miss_latency 12486511000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 513103 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 11460305000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 513103 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 449136 # number of replacements
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system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.520244 # Cycle average of tags in use
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system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 358125000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 316447 # number of writebacks
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system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 24978.142077 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 22978.142077 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 27426000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 25230000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1356569.911658 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 24978.142077 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
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system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 27426000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 25230000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 24978.142077 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 22978.142077 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 1489513763 # number of overall hits
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system.cpu.icache.overall_miss_latency 27426000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1098 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 25230000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 115 # number of replacements
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system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 891.566276 # Cycle average of tags in use
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system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 259752 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 5714544000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 259752 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857272000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 259752 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 194578 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 28424 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 3655388000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.853920 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 166154 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 1827694000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.853920 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 166154 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 59911 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 1318042000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 59911 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 659021000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 59911 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_misses 316447 # number of Writeback misses
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system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_mshr_misses 316447 # number of Writeback MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 3.182232 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 28424 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 9369932000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.937438 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 425906 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 4684966000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.937438 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 425906 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 454330 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 28424 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 9369932000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.937438 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 425906 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 4684966000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.937438 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 425906 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 18201 # number of replacements
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system.cpu.l2cache.sampled_refs 19574 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 8449.172652 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 62289 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 2070875212000 # number of cpu cycles simulated
|
|
system.cpu.num_insts 1489514860 # Number of instructions executed
|
|
system.cpu.num_refs 569359656 # Number of memory references
|
|
system.cpu.workload.PROG:num_syscalls 19 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|