4ed184eade
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
155 lines
5 KiB
C++
155 lines
5 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ben Nash
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*/
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/**
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* @file
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* Modifications for the FreeBSD kernel.
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* Based on kern/linux/linux_system.cc.
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*
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*/
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#include "arch/alpha/system.hh"
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#include "arch/alpha/freebsd/system.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/thread_context.hh"
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#include "mem/physical.hh"
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#include "mem/port.hh"
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#include "arch/isa_traits.hh"
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#include "sim/builder.hh"
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#include "sim/byteswap.hh"
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#include "arch/vtophys.hh"
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#define TIMER_FREQUENCY 1193180
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using namespace std;
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using namespace AlphaISA;
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FreebsdAlphaSystem::FreebsdAlphaSystem(Params *p)
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: AlphaSystem(p)
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{
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/**
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* Any time DELAY is called just skip the function.
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* Shouldn't we actually emulate the delay?
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*/
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skipDelayEvent = addKernelFuncEvent<SkipFuncEvent>("DELAY");
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skipCalibrateClocks =
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addKernelFuncEvent<SkipCalibrateClocksEvent>("calibrate_clocks");
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}
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FreebsdAlphaSystem::~FreebsdAlphaSystem()
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{
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delete skipDelayEvent;
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delete skipCalibrateClocks;
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}
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void
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FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
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{
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Addr ppc_vaddr = 0;
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Addr timer_vaddr = 0;
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ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1);
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timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2);
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virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
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virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
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}
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void
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FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
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{
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SkipFuncEvent::process(tc);
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((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
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Param<Tick> boot_cpu_frequency;
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SimObjectParam<PhysicalMemory *> physmem;
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SimpleEnumParam<System::MemoryMode> mem_mode;
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Param<string> kernel;
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Param<string> console;
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Param<string> pal;
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Param<string> boot_osflags;
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Param<string> readfile;
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Param<string> symbolfile;
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Param<unsigned int> init_param;
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Param<uint64_t> system_type;
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Param<uint64_t> system_rev;
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END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
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BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
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INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
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INIT_PARAM(physmem, "phsyical memory"),
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INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
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System::MemoryModeStrings),
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INIT_PARAM(kernel, "file that contains the kernel code"),
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INIT_PARAM(console, "file that contains the console code"),
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INIT_PARAM(pal, "file that contains palcode"),
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INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
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"a"),
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INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
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INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
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INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
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INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
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INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
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END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
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CREATE_SIM_OBJECT(FreebsdAlphaSystem)
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{
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AlphaSystem::Params *p = new AlphaSystem::Params;
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p->name = getInstanceName();
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p->boot_cpu_frequency = boot_cpu_frequency;
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p->physmem = physmem;
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p->mem_mode = mem_mode;
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p->kernel_path = kernel;
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p->console_path = console;
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p->palcode = pal;
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p->boot_osflags = boot_osflags;
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p->init_param = init_param;
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p->readfile = readfile;
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p->symbolfile = symbolfile;
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p->system_type = system_type;
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p->system_rev = system_rev;
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return new FreebsdAlphaSystem(p);
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}
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REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)
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