530 lines
59 KiB
Text
530 lines
59 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 152621 # Simulator instruction rate (inst/s)
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host_mem_usage 267940 # Number of bytes of host memory used
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host_seconds 12353.14 # Real time elapsed on the host
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host_tick_rate 64477641 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 1885343121 # Number of instructions simulated
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sim_seconds 0.796501 # Number of seconds simulated
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sim_ticks 796501458500 # Number of ticks simulated
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.BTBHits 295401459 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 412226769 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 2841374 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 40219938 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 399767362 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 521351365 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 53524846 # Number of times the RAS was used to get a target.
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system.cpu.commit.branchMispredicts 45744525 # The number of times a branch was mispredicted
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system.cpu.commit.branches 291352099 # Number of branches committed
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system.cpu.commit.bw_lim_events 67684151 # number cycles where commit BW limit reached
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.commitCommittedInsts 1885354137 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 211786 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 1014250107 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::samples 1409452320 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::mean 1.337650 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::stdev 2.030019 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::0 650998601 46.19% 46.19% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::1 389487426 27.63% 73.82% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::2 134882374 9.57% 83.39% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 70608044 5.01% 88.40% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::4 45598376 3.24% 91.64% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 18595515 1.32% 92.96% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::6 23751287 1.69% 94.64% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 7846546 0.56% 95.20% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::8 67684151 4.80% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::total 1409452320 # Number of insts commited each cycle
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system.cpu.commit.count 1885354137 # Number of instructions committed
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system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 41577833 # Number of function calls committed.
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system.cpu.commit.int_insts 1653713091 # Number of committed integer instructions.
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system.cpu.commit.loads 631390736 # Number of loads committed
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system.cpu.commit.membars 9986 # Number of memory barriers committed
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system.cpu.commit.refs 908389587 # Number of memory references committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu.committedInsts 1885343121 # Number of Instructions Simulated
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system.cpu.committedInsts_total 1885343121 # Number of Instructions Simulated
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system.cpu.cpi 0.844941 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.844941 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 16769 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_hits 16766 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.000179 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.ReadReq_accesses 708570219 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 34295.515999 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34092.262926 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 706637503 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 66283492500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002728 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1932716 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 469902 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 49870639500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002064 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1462814 # number of ReadReq MSHR misses
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system.cpu.dcache.StoreCondReq_accesses 13539 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits 13539 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 35038.454246 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32465.652371 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 276128758 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 28273229500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 806920 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 734193 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2361129500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 72727 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 15250 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 640.035711 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 61000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 985505897 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 34514.337671 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 982766261 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 94556722000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.002780 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 2739636 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 1204095 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 52231769000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.001558 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1535541 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_blocks::0 4094.850284 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 985505897 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 34514.337671 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 34015.222648 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 982766261 # number of overall hits
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system.cpu.dcache.overall_miss_latency 94556722000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.002780 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 2739636 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 1204095 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 52231769000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.001558 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1535541 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1531438 # number of replacements
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system.cpu.dcache.sampled_refs 1535534 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4094.850284 # Cycle average of tags in use
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system.cpu.dcache.total_refs 982796595 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 325357000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 107000 # number of writebacks
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system.cpu.decode.BlockedCycles 41214762 # Number of cycles decode is blocked
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system.cpu.decode.BranchMispred 11076 # Number of times decode detected a branch misprediction
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system.cpu.decode.BranchResolved 76817010 # Number of times decode resolved a branch
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system.cpu.decode.DecodedInsts 3347910149 # Number of instructions handled by decode
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system.cpu.decode.IdleCycles 727407671 # Number of cycles decode is idle
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system.cpu.decode.RunCycles 639439291 # Number of cycles decode is running
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system.cpu.decode.SquashCycles 146381913 # Number of cycles decode is squashing
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system.cpu.decode.SquashedInsts 20384 # Number of squashed instructions handled by decode
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system.cpu.decode.UnblockCycles 1390594 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.fetch.Branches 521351365 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 363393229 # Number of cache lines fetched
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system.cpu.fetch.Cycles 657902932 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 20866192 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 2539704301 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 47134046 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.327276 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 363393229 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 348926305 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.594287 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist::samples 1555834231 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.199016 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.044014 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 897966873 57.72% 57.72% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 37681413 2.42% 60.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 106074065 6.82% 66.96% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 61536348 3.96% 70.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 89725743 5.77% 76.68% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 53094530 3.41% 80.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 35033115 2.25% 82.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 45486191 2.92% 85.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 229235953 14.73% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1555834231 # Number of instructions fetched each cycle (Total)
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system.cpu.fp_regfile_reads 69468816 # number of floating regfile reads
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system.cpu.fp_regfile_writes 51556158 # number of floating regfile writes
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system.cpu.icache.ReadReq_accesses 363393229 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 9064.622402 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 5743.022314 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 363365607 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 250383000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 27622 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 464 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 155969000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 27158 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 13383.138890 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 363393229 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 9064.622402 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency
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system.cpu.icache.demand_hits 363365607 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 250383000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
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system.cpu.icache.demand_misses 27622 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 155969000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 27158 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_blocks::0 1549.568849 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.756625 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 363393229 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 9064.622402 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 5743.022314 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 363365607 # number of overall hits
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system.cpu.icache.overall_miss_latency 250383000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
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system.cpu.icache.overall_misses 27622 # number of overall misses
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system.cpu.icache.overall_mshr_hits 464 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 155969000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 27158 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 25561 # number of replacements
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system.cpu.icache.sampled_refs 27151 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1549.568849 # Cycle average of tags in use
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system.cpu.icache.total_refs 363365604 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 37168687 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.branchMispredicts 49895765 # Number of branch mispredicts detected at execute
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system.cpu.iew.exec_branches 348756775 # Number of branches executed
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system.cpu.iew.exec_nop 65493 # number of nop insts executed
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system.cpu.iew.exec_rate 1.479521 # Inst execution rate
|
|
system.cpu.iew.exec_refs 1131335426 # number of memory reference insts executed
|
|
system.cpu.iew.exec_stores 371509885 # Number of stores executed
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.iewBlockCycles 17394060 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewDispLoadInsts 927609743 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 231433 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewDispSquashedInsts 9066267 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 465231191 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 2899637757 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 759825541 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 94064084 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 2356880983 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 2638032 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 300 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 146381913 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 3942741 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread0.forwLoads 37882384 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1377639 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 2658197 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.squashedLoads 296219006 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.squashedStores 188232340 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 2658197 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 12410188 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 37485577 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.wb_consumers 2331728093 # num instructions consuming a value
|
|
system.cpu.iew.wb_count 2317489911 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_fanout 0.562854 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_producers 1312422376 # num instructions producing a value
|
|
system.cpu.iew.wb_rate 1.454793 # insts written-back per cycle
|
|
system.cpu.iew.wb_sent 2328575568 # cumulative count of insts sent to commit
|
|
system.cpu.int_regfile_reads 11595279326 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2306970978 # number of integer regfile writes
|
|
system.cpu.ipc 1.183515 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.183515 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1196267709 48.81% 48.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 11218358 0.46% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.60% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 6177350 0.25% 49.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 25435994 1.04% 50.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 793496500 32.38% 83.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 410088765 16.73% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2450945067 # Type of FU issued
|
|
system.cpu.iq.fp_alu_accesses 66027207 # Number of floating point alu accesses
|
|
system.cpu.iq.fp_inst_queue_reads 126553287 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57767686 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_writes 103061655 # Number of floating instruction queue writes
|
|
system.cpu.iq.fu_busy_cnt 75909773 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.030972 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 12391 0.02% 0.02% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 23967 0.03% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 52380943 69.00% 69.05% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 23492472 30.95% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.int_alu_accesses 2460827633 # Number of integer alu accesses
|
|
system.cpu.iq.int_inst_queue_reads 6419542643 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2259722225 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.int_inst_queue_writes 3795271933 # Number of integer instruction queue writes
|
|
system.cpu.iq.iqInstsAdded 2899328074 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 2450945067 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 244190 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 997384206 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 12461792 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 32404 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 2708929658 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.issued_per_cycle::samples 1555834231 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.575325 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.655347 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 573245192 36.84% 36.84% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 302098178 19.42% 56.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 270294423 17.37% 73.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 171510640 11.02% 84.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 147471533 9.48% 94.14% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 56656397 3.64% 97.78% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 24168420 1.55% 99.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 7568098 0.49% 99.82% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 2821350 0.18% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1555834231 # Number of insts issued each cycle
|
|
system.cpu.iq.rate 1.538569 # Inst issue rate
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.l2cache.ReadExReq_accesses 72720 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.683474 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.187900 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_hits 6637 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2279776500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.908732 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses 66083 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048651500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908732 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 66083 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_accesses 1489965 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34238.898726 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.364741 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_hits 75240 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_latency 48438626000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.949502 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 1414725 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_hits 21 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 43856340000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949488 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 1414704 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_accesses 7 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 0.714286 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.Writeback_accesses 107000 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits 107000 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0.055254 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 1562685 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 34250.491961 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 81877 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 50718402500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 0.947605 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 1480808 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 21 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 45904991500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.947591 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 1480787 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.occ_blocks::0 28973.685280 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_blocks::1 2993.152409 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_percent::0 0.884207 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::1 0.091344 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.overall_accesses 1562685 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 34250.491961 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.401476 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 81877 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 50718402500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.947605 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 1480808 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 21 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 45904991500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.947591 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 1480787 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 1479625 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 1512345 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 31966.837689 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 83563 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 66099 # number of writebacks
|
|
system.cpu.memDep0.conflictingLoads 97040035 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 144361648 # Number of conflicting stores.
|
|
system.cpu.memDep0.insertedLoads 927609743 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 465231191 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.misc_regfile_reads 3829379582 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 13780010 # number of misc regfile writes
|
|
system.cpu.numCycles 1593002918 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.rename.BlockCycles 25386531 # Number of cycles rename is blocking
|
|
system.cpu.rename.CommittedMaps 1993168535 # Number of HB maps that are committed
|
|
system.cpu.rename.IQFullEvents 3907408 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.IdleCycles 760805018 # Number of cycles rename is idle
|
|
system.cpu.rename.LSQFullEvents 7406697 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RenameLookups 15047193383 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RenamedInsts 3194680592 # Number of instructions processed by rename
|
|
system.cpu.rename.RenamedOperands 3359704809 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RunCycles 606032208 # Number of cycles rename is running
|
|
system.cpu.rename.SquashCycles 146381913 # Number of cycles rename is squashing
|
|
system.cpu.rename.UnblockCycles 13958692 # Number of cycles rename is unblocking
|
|
system.cpu.rename.UndoneMaps 1366536269 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.fp_rename_lookups 653924872 # Number of floating rename lookups
|
|
system.cpu.rename.int_rename_lookups 14393268511 # Number of integer rename lookups
|
|
system.cpu.rename.serializeStallCycles 3269869 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.serializingInsts 253997 # count of serializing insts renamed
|
|
system.cpu.rename.skidInsts 34813344 # count of insts added to the skid buffer
|
|
system.cpu.rename.tempSerializingInsts 254310 # count of temporary serializing insts renamed
|
|
system.cpu.rob.rob_reads 4241354068 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5945603467 # The number of ROB writes
|
|
system.cpu.timesIdled 1344843 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|