152 lines
4.3 KiB
C++
152 lines
4.3 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#ifndef __CPU_SIMPLE_ATOMIC_HH__
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#define __CPU_SIMPLE_ATOMIC_HH__
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#include "cpu/simple/base.hh"
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#include "params/AtomicSimpleCPU.hh"
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class AtomicSimpleCPU : public BaseSimpleCPU
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{
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public:
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AtomicSimpleCPU(AtomicSimpleCPUParams *params);
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virtual ~AtomicSimpleCPU();
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virtual void init();
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private:
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struct TickEvent : public Event
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{
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AtomicSimpleCPU *cpu;
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TickEvent(AtomicSimpleCPU *c);
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void process();
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const char *description() const;
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};
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TickEvent tickEvent;
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const int width;
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bool locked;
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const bool simulate_data_stalls;
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const bool simulate_inst_stalls;
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// main simulation loop (one cycle)
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void tick();
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class CpuPort : public Port
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{
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public:
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CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
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: Port(_name, _cpu), cpu(_cpu)
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{ }
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bool snoopRangeSent;
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protected:
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AtomicSimpleCPU *cpu;
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virtual bool recvTiming(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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virtual void recvStatusChange(Status status);
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virtual void recvRetry();
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop)
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{ resp.clear(); snoop = true; }
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};
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CpuPort icachePort;
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class DcachePort : public CpuPort
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{
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public:
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DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
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: CpuPort(_name, _cpu)
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{ }
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virtual void setPeer(Port *port);
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};
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DcachePort dcachePort;
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CpuPort physmemPort;
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bool hasPhysMemPort;
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Request ifetch_req;
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Request data_read_req;
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Request data_write_req;
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bool dcache_access;
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Tick dcache_latency;
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Range<Addr> physMemAddr;
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public:
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual void resume();
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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Fault writeBytes(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res);
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/**
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* Print state of address in memory system via PrintReq (for
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* debugging).
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*/
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void printAddr(Addr a);
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};
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#endif // __CPU_SIMPLE_ATOMIC_HH__
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