cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: Add the ability to simulate less than fully-associative opt caches. cpu/trace/reader/itx_reader.cc: Add writeback to the command list. --HG-- extra : convert_revision : a9c9c4be3358f4083d7e85772620441a3ad809db
206 lines
7.2 KiB
C++
206 lines
7.2 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a Intel ITX memory trace format reader.
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*/
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#include <sstream>
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#include "cpu/trace/reader/itx_reader.hh"
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#include "sim/builder.hh"
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#include "base/misc.hh" // for fatal
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using namespace std;
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ITXReader::ITXReader(const string &name, const string &filename)
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: MemTraceReader(name)
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{
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if (strcmp((filename.c_str() + filename.length() -3), ".gz") == 0) {
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// Compressed file, need to use a pipe to gzip.
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stringstream buf;
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buf << "gzip -d -c " << filename << endl;
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trace = popen(buf.str().c_str(), "r");
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} else {
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trace = fopen(filename.c_str(), "rb");
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}
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if (!trace) {
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fatal("Can't open file %s", filename);
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}
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traceFormat = 0;
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int c;
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for (int i = 0; i < 4; ++i) {
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c = getc(trace);
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if (c == EOF) {
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fatal("Unexpected end of trace file.");
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}
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traceFormat |= (c & 0xff) << (8 * i);
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}
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if (traceFormat > 2)
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fatal("Invalid trace format.");
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}
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Tick
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ITXReader::getNextReq(MemReqPtr &req)
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{
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MemReqPtr tmp_req = new MemReq();
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bool phys_val;
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do {
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int c = getc(trace);
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if (c != EOF) {
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// Decode first byte
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// phys_val<1> | type <2:0> | size <3:0>
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phys_val = c & 0x80;
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tmp_req->size = (c & 0x0f) + 1;
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int type = (c & 0x70) >> 4;
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// Could be a compressed instruction entry, expand if necessary
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if (type == ITXCodeComp) {
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if (traceFormat != 2) {
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fatal("Compressed code entry in non CompCode trace.");
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}
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if (!codeVirtValid) {
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fatal("Corrupt CodeComp entry.");
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}
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tmp_req->vaddr = codeVirtAddr;
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codeVirtAddr += tmp_req->size;
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if (phys_val) {
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if (!codePhysValid) {
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fatal("Corrupt CodeComp entry.");
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}
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tmp_req->paddr = codePhysAddr;
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if (((tmp_req->paddr & 0xfff) + tmp_req->size) & ~0xfff) {
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// Crossed page boundary, next physical address is
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// invalid
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codePhysValid = false;
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} else {
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codePhysAddr += tmp_req->size;
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}
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assert(tmp_req->paddr >> 36 == 0);
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} else {
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codePhysValid = false;
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}
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type = ITXCode;
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tmp_req->cmd = Read;
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} else {
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// Normal entry
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tmp_req->vaddr = 0;
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for (int i = 0; i < 4; ++i) {
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c = getc(trace);
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if (c == EOF) {
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fatal("Unexpected end of trace file.");
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}
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tmp_req->vaddr |= (c & 0xff) << (8 * i);
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}
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if (type == ITXCode) {
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codeVirtAddr = tmp_req->vaddr + tmp_req->size;
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codeVirtValid = true;
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}
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tmp_req->paddr = 0;
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if (phys_val) {
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c = getc(trace);
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if (c == EOF) {
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fatal("Unexpected end of trace file.");
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}
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// Get the page offset from the virtual address.
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tmp_req->paddr = tmp_req->vaddr & 0xfff;
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tmp_req->paddr |= (c & 0xf0) << 8;
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tmp_req->paddr |= (Addr)(c & 0x0f) << 32;
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for (int i = 2; i < 4; ++i) {
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c = getc(trace);
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if (c == EOF) {
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fatal("Unexpected end of trace file.");
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}
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tmp_req->paddr |= (Addr)(c & 0xff) << (8 * i);
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}
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if (type == ITXCode) {
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if (((tmp_req->paddr & 0xfff) + tmp_req->size)
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& ~0xfff) {
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// Crossing the page boundary, next physical
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// address isn't valid
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codePhysValid = false;
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} else {
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codePhysAddr = tmp_req->paddr + tmp_req->size;
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codePhysValid = true;
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}
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}
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assert(tmp_req->paddr >> 36 == 0);
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} else if (type == ITXCode) {
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codePhysValid = false;
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}
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switch(type) {
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case ITXRead:
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tmp_req->cmd = Read;
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break;
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case ITXWrite:
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tmp_req->cmd = Write;
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break;
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case ITXWriteback:
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tmp_req->cmd = Writeback;
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break;
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case ITXCode:
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tmp_req->cmd = Read;
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tmp_req->flags |= INST_READ;
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break;
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default:
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fatal("Unknown ITX type");
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}
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}
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} else {
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// EOF need to return a null request
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MemReqPtr null_req;
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req = null_req;
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return 0;
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}
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} while (!phys_val);
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req = tmp_req;
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assert(!req || (req->paddr >> 36) == 0);
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return 0;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
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Param<string> filename;
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END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
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BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
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INIT_PARAM(filename, "trace file")
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END_INIT_SIM_OBJECT_PARAMS(ITXReader)
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CREATE_SIM_OBJECT(ITXReader)
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{
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return new ITXReader(getInstanceName(), filename);
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}
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REGISTER_SIM_OBJECT("ITXReader", ITXReader)
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