| .. |
|
resources
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
comm.hh
|
InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
|
2009-03-04 13:17:05 -05:00 |
|
cpu.cc
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
cpu.hh
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
first_stage.cc
|
inorder-fetch: update model to use predecoder
|
2009-05-12 15:01:15 -04:00 |
|
first_stage.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
inorder_cpu_builder.cc
|
Remove unused functions/comments cluttering up the code.
|
2009-03-04 13:17:08 -05:00 |
|
inorder_dyn_inst.cc
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
inorder_dyn_inst.hh
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
inorder_trace.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
inorder_trace.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
InOrderCPU.py
|
InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
|
2009-03-04 13:17:05 -05:00 |
|
InOrderTrace.py
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
params.hh
|
Remove unused functions/comments cluttering up the code.
|
2009-03-04 13:17:08 -05:00 |
|
pipeline_stage.cc
|
inorder-fetch: update model to use predecoder
|
2009-05-12 15:01:15 -04:00 |
|
pipeline_stage.hh
|
stats: Fix all stats usages to deal with template fixes
|
2009-03-05 19:09:53 -08:00 |
|
pipeline_traits.5stage.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.5stage.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.9stage.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.9stage.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.9stage.smt2.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.9stage.smt2.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
pipeline_traits.cc
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
pipeline_traits.hh
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
reg_dep_map.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
reg_dep_map.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
resource.cc
|
inorder-resources: delete events
|
2009-05-12 15:01:16 -04:00 |
|
resource.hh
|
inorder-resources: delete events
|
2009-05-12 15:01:16 -04:00 |
|
resource_pool.9stage.cc
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
|
resource_pool.cc
|
inorder-resources: delete events
|
2009-05-12 15:01:16 -04:00 |
|
resource_pool.hh
|
inorder-resources: delete events
|
2009-05-12 15:01:16 -04:00 |
|
SConscript
|
inorder-tlb-cunit: merge the TLB as implicit to any memory access
|
2009-05-12 15:01:16 -04:00 |
|
SConsopts
|
cpus: add InOrderCPU to default build
|
2009-05-12 20:55:21 -04:00 |
|
thread_context.cc
|
Get rid of the Unallocated thread context state.
|
2009-04-15 13:13:47 -07:00 |
|
thread_context.hh
|
inorder-alpha-port: initial inorder support of ALPHA
|
2009-05-12 15:01:13 -04:00 |
|
thread_state.hh
|
InOrder: Import new inorder CPU model from MIPS.
|
2009-02-10 15:49:29 -08:00 |
