64c0d82dec
configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
223 lines
8.4 KiB
Python
223 lines
8.4 KiB
Python
# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Lisa Hsu
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from os import getcwd
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from os.path import join as joinpath
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import m5
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from m5.objects import *
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m5.AddToPath('../common')
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from Caches import L1Cache
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def setCPUClass(options):
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atomic = False
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if options.timing:
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TmpClass = TimingSimpleCPU
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elif options.detailed:
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TmpClass = DerivO3CPU
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else:
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TmpClass = AtomicSimpleCPU
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atomic = True
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CPUClass = None
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test_mem_mode = 'atomic'
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if not atomic:
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if options.checkpoint_restore:
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CPUClass = TmpClass
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TmpClass = AtomicSimpleCPU
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else:
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test_mem_mode = 'timing'
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return (TmpClass, test_mem_mode, CPUClass)
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def run(options, root, testsys, cpu_class):
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if options.maxtick:
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maxtick = options.maxtick
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elif options.maxtime:
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simtime = int(options.maxtime * root.clock.value)
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print "simulating for: ", simtime
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maxtick = simtime
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else:
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maxtick = m5.MaxTick
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if options.checkpoint_dir:
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cptdir = options.checkpoint_dir
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else:
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cptdir = getcwd()
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np = options.num_cpus
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max_checkpoints = options.max_checkpoints
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switch_cpus = None
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if cpu_class:
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switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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for i in xrange(np):
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switch_cpus[i].system = testsys
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if not m5.build_env['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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if options.caches:
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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switch_cpus[i].connectMemPorts(testsys.membus)
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root.switch_cpus = switch_cpus
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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if options.standard_switch:
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switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
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for i in xrange(np)]
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switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
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for i in xrange(np)]
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for i in xrange(np):
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switch_cpus[i].system = testsys
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switch_cpus_1[i].system = testsys
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if not m5.build_env['FULL_SYSTEM']:
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switch_cpus[i].workload = testsys.cpu[i].workload
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switch_cpus_1[i].workload = testsys.cpu[i].workload
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switch_cpus[i].clock = testsys.cpu[0].clock
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switch_cpus_1[i].clock = testsys.cpu[0].clock
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if options.caches:
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switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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switch_cpus[i].connectMemPorts(testsys.membus)
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else:
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# O3 CPU must have a cache to work.
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switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
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L1Cache(size = '64kB'))
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switch_cpus_1[i].connectMemPorts(testsys.membus)
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root.switch_cpus = switch_cpus
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root.switch_cpus_1 = switch_cpus_1
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switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
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switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
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m5.instantiate(root)
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if options.checkpoint_restore:
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from os.path import isdir
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from os import listdir
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import re
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if not isdir(cptdir):
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m5.panic("checkpoint dir %s does not exist!" % cptdir)
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dirs = listdir(cptdir)
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expr = re.compile('cpt.([0-9]*)')
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cpts = []
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for dir in dirs:
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match = expr.match(dir)
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if match:
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cpts.append(match.group(1))
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cpts.sort(lambda a,b: cmp(long(a), long(b)))
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cpt_num = options.checkpoint_restore
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if cpt_num > len(cpts):
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m5.panic('Checkpoint %d not found' % cpt_num)
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m5.restoreCheckpoint(root,
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joinpath(cptdir, "cpt.%s" % cpts[cpt_num - 1]))
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if options.standard_switch or cpu_class:
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exit_event = m5.simulate(10000)
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## when you change to Timing (or Atomic), you halt the system given
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## as argument. When you are finished with the system changes
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## (including switchCpus), you must resume the system manually.
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## You DON'T need to resume after just switching CPUs if you haven't
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## changed anything on the system level.
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m5.changeToTiming(testsys)
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m5.switchCpus(switch_cpu_list)
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m5.resume(testsys)
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if options.standard_switch:
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exit_event = m5.simulate(options.warmup)
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m5.switchCpus(switch_cpu_list1)
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num_checkpoints = 0
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exit_cause = ''
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## Checkpoints being taken via the command line at <when> and at subsequent
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## periods of <period>. Checkpoint instructions received from the benchmark running
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## are ignored and skipped in favor of command line checkpoint instructions.
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if options.take_checkpoints:
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[when, period] = options.take_checkpoints.split(",", 1)
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when = int(when)
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period = int(period)
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exit_event = m5.simulate(when)
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while exit_event.getCause() == "checkpoint":
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exit_event = m5.simulate(when - m5.curTick())
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if exit_event.getCause() == "simulate() limit reached":
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m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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sim_ticks = when
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exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
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while num_checkpoints < max_checkpoints:
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if (sim_ticks + period) > maxtick:
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exit_event = m5.simulate(maxtick - sim_ticks)
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exit_cause = exit_event.getCause()
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break
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else:
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exit_event = m5.simulate(period)
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sim_ticks += period
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while exit_event.getCause() == "checkpoint":
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exit_event = m5.simulate(sim_ticks - m5.curTick())
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if exit_event.getCause() == "simulate() limit reached":
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m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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else: #no checkpoints being taken via this script
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exit_event = m5.simulate(maxtick)
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while exit_event.getCause() == "checkpoint":
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m5.checkpoint(root, joinpath(cptdir, "cpt.%d"))
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num_checkpoints += 1
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if num_checkpoints == max_checkpoints:
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exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
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break
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exit_event = m5.simulate(maxtick - m5.curTick())
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exit_cause = exit_event.getCause()
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if exit_cause == '':
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exit_cause = exit_event.getCause()
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print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
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