gem5/src
Gabe Black ced6cbcccf X86: Create a base enum value for indexing into a region of the miscregs.
This lets you index into a group of registers without having to know
explicitly which one is the lowest in that group.

--HG--
extra : convert_revision : e3cad25a1c5910955204c37177b049ca9834cfd9
2007-08-04 20:07:42 -07:00
..
arch X86: Create a base enum value for indexing into a region of the miscregs. 2007-08-04 20:07:42 -07:00
base Output: Make OutputDirectory::create() be able to create binary files. 2007-08-02 14:40:56 -04:00
cpu X86: Reorganize the native tracing code. 2007-08-01 12:01:51 -07:00
dev Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Arguments: Get rid of duplicate code for the Arguments class in each architecture. 2007-08-01 16:59:14 -04:00
mem Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
python python: Improve support for python calling back to C++ member functions. 2007-08-02 22:50:02 -07:00
sim python: Improve support for python calling back to C++ member functions. 2007-08-02 22:50:02 -07:00
unittest Quick program to time how long ccprintf takes to write 2007-02-07 22:02:09 -08:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Add a new SCons option called EXTRAS that allows you to include stuff in 2007-07-25 18:21:11 -07:00